US5469109A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for programming anti-fuse devices
Assignee: QuickLogic Corp
•
Filing: 1995-02-09
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Granted: 1995-11-21
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Expires: 2015-02-09
Abstract
Abstract Improved apparatus and methods for programming anti-fuse devices utilized in programmable semiconductor chips are described. An anti-fuse device circuit is disclosed wherein an anti-fuse device is connected between two programming transistors, and each programming transistor is connected to a separate voltage supply bus and to a control bus network having, for example, a common control bus or separate control buses. Interconnection structures of anti-fuse devices can be formed and a targeted anti-fuse device can be programmed by connecting a programming voltage to the first associated supply bus, by connecting another voltage or ground potential to the second associated supply bus, and by turning on the appropriate control bus line or lines so that the programming transistors conduct to provide a voltage differential across the targeted anti-fuse device. Several anti-fuse device interconnection embodiments are discussed, and the choice of a particular scheme to use for fabricating a programmable chip is dependent on the desired design features and on ease of software implementation.
Inventors
- 👤 John O. Paivinen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; G; G11; G11C; G11C17/00; G11C17/14; G11C17/18
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
197 words
A circuit for selectively programming anti-fuse devices that are connected to form an array of anti-fuse devices, to minimize signal race conditions of logic signals, comprising: a plurality of anti-fuse devices connected in series strings to form columns of anti-fuse devices in the array, each anti-fuse device having a first node at a first end and second node at a second end; a first voltage supply bus; a second voltage supply bus; a plurality of first and second transistors each having a control terminal for placing the transistor in an ON condition, wherein each first transistor connects the first node of an anti-fuse device to the first voltage supply bus and each second transistor connects the second node of an anti-fuse device to the second voltage supply bus; a plurality of control bus lines connected to the control terminals of each of the plurality of first and second transistors, operable to turn ON selected transistors; and a control logic circuit connected to the control bus lines operable to program selected anti-fuse devices such that a voltage appears across an anti-fuse device and a current is delivered to that anti-fuse device to program it to a desired impedance.
Claim 2
Dependent Claim
197 words
A circuit for selectively programming anti-fuse devices that are connected to form an array of anti-fuse devices, to minimize signal race conditions of logic signals, comprising: a plurality of anti-fuse devices connected in series strings to form columns of anti-fuse devices in the array, each anti-fuse device having a first node at a first end and second node at a second end; a first voltage supply bus; a second voltage supply bus; a plurality of first and second transistors each having a control terminal for placing the transistor in an ON condition, wherein each first transistor connects the first node of an anti-fuse device to the first voltage supply bus and each second transistor connects the second node of an anti-fuse device to the second voltage supply bus; a plurality of control bus lines connected to the control terminals of each of the plurality of first and second transistors, operable to turn ON selected transistors; and a control logic circuit connected to the control bus lines operable to program selected anti-fuse devices such that a voltage appears across an anti-fuse device and a current is delivered to that anti-fuse device to program it to a desired impedance.
Claim 3
Dependent Claim
50 words
The apparatus of claim 1, wherein the control logic circuit comprises: a first logic control means having a first voltage driver circuit; and a second logic control means having a second voltage driver circuit, wherein the first and second logic control means operate cooperatively to program a selected anti-fuse device.
Claim 4
Dependent Claim
41 words
The apparatus of claim 1, wherein the control logic circuit comprises: first and a second voltage driver circuits for turning ON a first and a second transistor connected to adjacent nodes of a selected anti-fuse device, to program that anti-fuse device.
Claim 5
Dependent Claim
30 words
The apparatus of claim 1, further comprising: a first voltage detector for monitoring the first voltage supply bus; and a second voltage detector for monitoring the second voltage supply bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-20 | 1999-05-22 | 1999-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-20 | 2003-05-22 | 2003-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-20 | 2007-05-22 | 2007-11-21 | $7700.00 | Window Closed / Lapsed |