Contact-free floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates

Claim 2

An electrically-erasable, electrically-programmable read-only memory cell formed at a face of a layer of semiconductor of a first conductivity type, comprising: first and second diffused region formed at said face to be of a second conductivity type opposite said first conductivity type, said first and second diffused regions spaced by a channel area; a floating gate conductor having an upper surface, a lower surface opposing said upper surface, and side extending between said upper and lower surfaces, said lower surface of said floating gate insulatively adjacent said channel area; a first control gate conductor, extending in a lengthwise direction and having an upper surface, a lower surface opposing said upper surface, and sides extending between said upper and lower surfaces, said lower surface of said first control gate conductor insulatively adjacent said upper surface of said floating gate; and a second control gate conductor having a lower surface and an upper surface, lateral sides of said second control gate conductor extending between said upper and lower surfaces of said second control gate, at least one side of said second control gate conductor substantially laterally spaced from a respective side of said first control gate conductor, said lower surface of said second control gate conductor conformably contacting substantially all of the extended length of said upper surface of said first control gate conductor.

Claim 3

The memory cell of claim 1, and further comprising insulator formed adjacent said sides of said floating gate.

Claim 4

The memory cell of claim 2, wherein said insulator is further formed adjacent said sides of said first control gate conductor.

Claim 5

The memory cell of claim 3, wherein said insulator comprises thermally grown oxide.

Claim 6

The memory cell of claim 1, and further comprising silicided regions formed adjacent said first and second diffused regions.

Claim 7

The memory cell of claim 1, wherein said conductors comprise heavily doped polycrystalline silicon.

Claim 8

The memory cell of claim 1, wherein said floating gate conductor and said first control gate conductor are formed of heavily doped polycrystalline silicon and said second control gate conductor is formed of silicided polycrystalline silicon.

Claim 9

The memory cell of claim 1, wherein said floating gate conductor and said first control gate conductor are formed of heavily doped polycrystalline silicon and said second control gate conductor is formed of a metal.

Claim 10

The memory cell of claim 8, wherein said metal is refractory metal.

Claim 11

The memory cell of claim 1, wherein said first and second diffused regions are buried under relatively thick insulator layers.

Claim 12

The memory cell of claim 10, wherein said floating gate and said first control gate extend over portions of said insulator layers.

Claim 13

An array of electrically-programmable, electrically-erasable read-only memory cells formed in columns and in rows, at an angle to said columns, at the face of a layer of semiconductor of a first conductivity type, comprising: a plurality of parallel elongated silicided diffused regions spaced by a plurality of elongated channel areas, adjacent ones of said diffused regions forming a column of cells; for each cell, a thin insulator tunneling window formed in a respective one of said channel areas adjacent a respective one of said diffused regions; for each cell, a floating gate conductor having an upper surface, a lower surface opposing said upper surface and sides extending between said upper and lower surfaces, said lower surface of said floating gate conductor formed insulatively adjacent a portion of a respective one of said channel regions and adjacent said respective thin tunneling window of said cell; for each cell, a control gate conductor extending in a lengthwise direction and having an upper surface, a lower surface opposing said upper surface and sides extending between said upper and lower surfaces, said lower surface of said control gate conductor insulatively adjacent said upper surface of said floating gate conductor of said cell; and a plurality of wordline conductors, each having a lower surface and an upper surface, lateral sides of each wordline conductor extending between said upper and lower surfaces of said wordline conductor, said wordline conductors forming a plurality of spaced apart rows at an angle to said columns, said lower surface of each wordline conductor formed to contact substantially all of the extended lengths of said upper surfaces of said control gate conductors in respective ones of said rows, at least one lateral side of each of said wordline conductors substantially laterally spaced from a respective one of said sides of said control gate conductors.

Claim 14

An array of electrically-programmable, electrically-erasable read-only memory cells formed in columns and in rows, at an angle to said columns, at the face of a layer of semiconductor of a first conductivity type, comprising: a plurality of parallel elongated silicided diffused regions spaced by a plurality of elongated channel areas, adjacent ones of said diffused regions forming a column of cells; for each cell, a thin insulator tunneling window formed in a respective one of said channel areas adjacent a respective one of said diffused regions; for each cell, a floating gate conductor having an upper surface, a lower surface opposing said upper surface and sides extending between said upper and lower surfaces, said lower surface of said floating gate conductor formed insulatively adjacent a portion of a respective one of said channel regions and adjacent said respective thin tunneling window of said cell; for each cell, a control gate conductor extending in a lengthwise direction and having an upper surface, a lower surface opposing said upper surface and sides extending between said upper and lower surfaces, said lower surface of said control gate conductor insulatively adjacent said upper surface of said floating gate conductor of said cell; and a plurality of wordline conductors, each having a lower surface and an upper surface, lateral sides of each wordline conductor extending between said upper and lower surfaces of said wordline conductor, said wordline conductors forming a plurality of spaced apart rows at an angle to said columns, said lower surface of each wordline conductor formed to contact substantially all of the extended lengths of said upper surfaces of said control gate conductors in respective ones of said rows, at least one lateral side of each of said wordline conductors substantially laterally spaced from a respective one of said sides of said control gate conductors.

Claim 15

The array of claim 12, and further comprising insulator formed on said sides of said floating conductors.

Claim 16

The array of claim 13, and further comprising insulator disposed on said sides of said control gate conductors.

Claim 17

The array of claim 12, wherein said floating gate conductors and said control gate conductors are formed of highly doped polycrystalline silicon.

Claim 18

The array of claim 15, wherein said wordline conductors are formed of highly doped polycrystalline silicon.

Claim 19

The array of claim 16, wherein said wordline conductors comprise a metal.

Claim 20

The array of claim 14, wherein said wordline conductors comprise refractory metal.

Claim 21

The array of claim 12, and further comprising relatively thick oxide regions formed at said face of said semiconductor and separating adjacent ones of said rows.

Claim 22

The array of claim 12, and further comprising relatively thick oxide regions overlying said elongated diffused regions.

Claim 23

The array of claim 20, wherein said floating gate conductors and said control gate conductors extend over portions of adjacent ones of said thick oxide regions.

Claim 24

An electrically-erasable, electrically-programmable read-only memory cell formed at a face of a layer of semiconductor of a first conductivity type, comprising: first and second diffused region formed at said face to be of a second conductivity type opposite said first conductivity type, said first and second diffused regions spaced by a channel area; a floating gate conductor having an upper surface, a lower surface opposing said upper surface, and side extending between said upper and lower surfaces, said lower surface of said floating gate disposed insulatively adjacent said channel area; a first control gate conductor having an upper surface, a lower surface opposing said upper surface, and sides extending between said upper and lower surfaces of said first control gate, said lower surface of said first control gate conductor insulatively adjacent said upper surface of said floating gate; a second control gate conductor extending in a lengthwise direction and comprising polycrystalline silicon and having a lower surface, an upper surface opposing said lower surface, and sides extending between said upper and lower surfaces of said second control gate, said lower surface of said second control gate conductor contacting substantially all of the extended length of said upper surface of said first control gate conductor, at least one side of said second control gate conductor substantially laterally spaced from a respective side of said first control gate conductor.

Claim 25

An electrically-erasable, electrically-programmable read-only memory cell formed at a face of a layer of semiconductor of a first conductivity type, comprising: first and second diffused region formed at said face to be of a second conductivity type opposite said first conductivity type, said first and second diffused regions spaced by a channel area; a floating gate conductor having an upper surface, a lower surface opposing said upper surface, and side extending between said upper and lower surfaces, said lower surface of said floating gate disposed insulatively adjacent said channel area; a first control gate conductor having an upper surface, a lower surface opposing said upper surface, and sides extending between said upper and lower surfaces of said first control gate, said lower surface of said first control gate conductor insulatively adjacent said upper surface of said floating gate; a second control gate conductor extending in a lengthwise direction and comprising polycrystalline silicon and having a lower surface, an upper surface opposing said lower surface, and sides extending between said upper and lower surfaces of said second control gate, said lower surface of said second control gate conductor contacting substantially all of the extended length of said upper surface of said first control gate conductor, at least one side of said second control gate conductor substantially laterally spaced from a respective side of said first control gate conductor.

Claim 26

The memory cell of claim 22, and further comprising insulator formed adjacent said sides of said floating gate.

Claim 27

The memory cell of claim 23, wherein said insulator is further formed adjacent said sides of said first control gate conductor.

Claim 28

The memory cell of claim 24, wherein said insulator comprises thermally grown oxide.

Claim 29

The memory cell of claim 22, and further comprising silicided regions formed adjacent said first and second diffused regions.

Claim 30

The memory cell of claim 22, wherein said conductors comprise heavily doped polycrystalline silicon.

Claim 31

The memory cell of claim 22, wherein said floating gate conductor and said first control gate conductor are formed of heavily doped polycrystalline silicon and said second control gate conductor is formed of silicided polycrystalline silicon.

Claim 32

The memory cell of claim 22, wherein said first and second diffused regions are buried under relatively thick insulator layers.

Claim 33

The memory cell of claim 29, wherein said floating gate conductor and said first control gate conductor extend over portions of said insulator layers.

Claim 34

An array of electrically-programmable, electrically-erasable read-only memory cells formed in columns and in rows, at an angle to said columns, at a face of a layer of semiconductor of a first conductivity type, comprising: a plurality of parallel elongated diffused regions spaced by a plurality of elongated channel areas, adjacent ones of said diffused regions forming a column of cells; for each cell, a thin insulator tunneling window formed in a respective one of said channel areas adjacent a respective one of said diffused regions; for each cell, a floating gate conductor having an upper surface, a lower surface opposing said upper surface, and sides extending between said upper and lower surfaces, said lower surface of said floating gate conductor formed insulatively adjacent a portion of a respective one of said channel regions and adjacent said respective thin tunneling window of said cell; for each cell, a control gate conductor having an upper surface, a lower surface opposing said upper surface and sides extending between said upper and lower surfaces, said lower surface of said control gate insulatively adjacent said upper surface of said floating gate of said cell; and a plurality of wordline conductors comprising polycrystalline silicon, each having a lower surface, an upper surface opposing said lower surface, and sides extending between said upper and lower surfaces of said wordline, and forming a plurality of spaced apart rows at an angle to said columns, said lower surface of each wordline conductor formed to contact said upper surfaces of said control gate conductors in respective ones of said rows, at least one side of said wordline substantially laterally spaced from a corresponding side of at least one control gate conductor in said respective row.

Claim 35

An array of electrically-programmable, electrically-erasable read-only memory cells formed in columns and in rows, at an angle to said columns, at a face of a layer of semiconductor of a first conductivity type, comprising: a plurality of parallel elongated diffused regions spaced by a plurality of elongated channel areas, adjacent ones of said diffused regions forming a column of cells; for each cell, a thin insulator tunneling window formed in a respective one of said channel areas adjacent a respective one of said diffused regions; for each cell, a floating gate conductor having an upper surface, a lower surface opposing said upper surface, and sides extending between said upper and lower surfaces, said lower surface of said floating gate conductor formed insulatively adjacent a portion of a respective one of said channel regions and adjacent said respective thin tunneling window of said cell; for each cell, a control gate conductor having an upper surface, a lower surface opposing said upper surface and sides extending between said upper and lower surfaces, said lower surface of said control gate insulatively adjacent said upper surface of said floating gate of said cell; and a plurality of wordline conductors comprising polycrystalline silicon, each having a lower surface, an upper surface opposing said lower surface, and sides extending between said upper and lower surfaces of said wordline, and forming a plurality of spaced apart rows at an angle to said columns, said lower surface of each wordline conductor formed to contact said upper surfaces of said control gate conductors in respective ones of said rows, at least one side of said wordline substantially laterally spaced from a corresponding side of at least one control gate conductor in said respective row.

Claim 36

The array of claim 31, and further comprising insulator formed on said sides of said floating gate conductors.

Claim 37

The array of claim 31, and further comprising insulator disposed on said sides of said control gate conductors.

Claim 38

The array of claim 31, wherein said floating gate conductors and said control gate conductors are formed of highly doped polycrystalline silicon.

Claim 39

The array of claim 31, wherein said wordline conductors are formed of silicided polycrystalline silicon.

Claim 40

The array of claim 31, and further comprising relatively thick oxide regions formed at said face of said semiconductor and separating adjacent ones of said rows.

Claim 41

The array of claim 31, and further comprising relatively thick oxide regions overlying said elongated diffused regions.

Claim 42

The array of claim 37, wherein said floating gate conductors and said control gate conductors extend over portions of adjacent ones of said thick oxide regions.