US5023680A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates
Assignee: Texas Instruments Inc
•
Filing: 1988-11-10
•
Granted: 1991-06-11
•
Expires: 2008-11-10
Abstract
Abstract A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide regions. A thick field oxide strip separates each ground conductor/bitline pair. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The four sides of the floating gates are defined with a single patterning step. The resulting structure is a dense cross-point array of programmable memory cells.
Inventors
- 👤 Manzur Gill
- 👤 Howard L. Tigelaar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:25
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/686; H10B; H10B69/00; H10D30/683
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
252 words
A non-volatile memory cell array, comprising: a plurality of parallel conductors including source-drain regions formed in a face of a semiconductor substrate, each of said conductors being a heavily-doped region of second conductivity-type opposite that of a first conductivity-type of the underlying material of said semiconductor substrate, each of said source-drain regions being spaced from at least one other said source-drain region on said face by a channel area, wherein said parallel conductors are formed in groups of three conductors; thick field oxide regions located at the face of said semiconductor substrate between adjacent ones of said conductors and between adjacent ones of said channel areas; thick field oxide strips located in the face of said semiconductor substrate between each said group of three parallel conductors; a floating gate over each said channel are, the floating gate being separated from said channel area of said face by a gate insulator layer, wherein said floating gate extends over a part of each adjacent thick field oxide region, the extensions being in directions substantially at right angles to the direction of said parallel conductors; a control gate extending along said face over said floating gate, the control gate being separated from said floating gate by an inter-level dielectric layer; and a plurality of separately formed wordlines contacting said control gates and extending over said control gates in a direction substantially at right angle to the direction of said parallel conductors; wherein each of said conductors including said source-drain regions also includes a silicided region.
Claim 2
Dependent Claim
252 words
A non-volatile memory cell array, comprising: a plurality of parallel conductors including source-drain regions formed in a face of a semiconductor substrate, each of said conductors being a heavily-doped region of second conductivity-type opposite that of a first conductivity-type of the underlying material of said semiconductor substrate, each of said source-drain regions being spaced from at least one other said source-drain region on said face by a channel area, wherein said parallel conductors are formed in groups of three conductors; thick field oxide regions located at the face of said semiconductor substrate between adjacent ones of said conductors and between adjacent ones of said channel areas; thick field oxide strips located in the face of said semiconductor substrate between each said group of three parallel conductors; a floating gate over each said channel are, the floating gate being separated from said channel area of said face by a gate insulator layer, wherein said floating gate extends over a part of each adjacent thick field oxide region, the extensions being in directions substantially at right angles to the direction of said parallel conductors; a control gate extending along said face over said floating gate, the control gate being separated from said floating gate by an inter-level dielectric layer; and a plurality of separately formed wordlines contacting said control gates and extending over said control gates in a direction substantially at right angle to the direction of said parallel conductors; wherein each of said conductors including said source-drain regions also includes a silicided region.
Claim 3
Dependent Claim
26 words
A memory cell array according to claim 1 including insulating oxide strips on said face between said wordlines and over portions of said insulating oxide regions.
Claim 4
Dependent Claim
26 words
A memory cell array according to claim 1 wherein said semiconductor substrate is silicon, and said first conductivity-type is P-type and said second conductivity-type is N-type.
Claim 5
Dependent Claim
22 words
A memory cell array according to claim 1 wherein a said floating gate and a said control gate are polycrystalline silicon layers.
Claim 6
Dependent Claim
15 words
A memory cell array according to claim 1 wherein a said wordline is polycrystalline silicon.
Claim 7
Dependent Claim
16 words
A memory cell array according to claim 1 wherein a said wordline is silicided polycrystalline silicon.
Claim 8
Dependent Claim
14 words
A memory cell array according to claim 1 wherein a said wordline is metal.
Claim 9
Dependent Claim
15 words
A memory cell array according to claim 1 wherein a said wordline is refractory metal.
Claim 10
Dependent Claim
18 words
A memory cell array according to claim 1 wherein a said wordline is layered refractory metal and polysilicon.
Claim 11
Dependent Claim
30 words
A memory cell array according to claim 1 wherein a capacitance associated with a said inter-level dielectric layer is greater than a capacitance associated with a said gate insulator layer.
Claim 12
Dependent Claim
16 words
A memory cell array according to claim 1 wherein said inter-level dielectric layer includes silicon oxide.
Claim 13
Dependent Claim
15 words
A memory cell array according to claim 1 wherein said inter-level dielectric layer includes oxide-nitride-oxide.
Claim 14
Dependent Claim
16 words
A memory cell array according to claim 1 wherein said inter-level dielectric layer includes aluminum oxide.
Claim 15
Dependent Claim
16 words
A memory cell array according to claim 1 wherein said inter-level dielectric layer includes aluminum nitride.
Claim 16
Dependent Claim
15 words
A memory cell according to claim 1 wherein said inter-level dielectric layer includes tantalum pentoxide.
Claim 17
Dependent Claim
20 words
A memory cell array according to claim 1 including sidewall oxide spacers adjacent said control gate and said floating gate.
Claim 18
Dependent Claim
25 words
A memory cell array according to claim 1 wherein at least one of said source-drain regions adjacent each said channel area has graded impurity concentrations.
Claim 19
Dependent Claim
17 words
A memory cell array according to claim 1 wherein said gate insulator layer includes a tunnelling region.
Claim 20
Dependent Claim
18 words
A memory cell array according to claim 1 wherein said underlying channel stop regions are doped with boron.
Claim 21
Dependent Claim
29 words
A memory cell array according to claim 1, including channel stop regions underlying at least one of said thick field oxide regions and of said thick field oxide strips.
Claim 22
Dependent Claim
20 words
A memory cell array according to claim 1 wherein said separately formed wordlines extend over said thick field oxide regions.
Claim 23
Dependent Claim
24 words
A memory cell array according to claim 1 wherein the four sides of said floating gates are covered by a single-step thermally grown oxide.
Claim 24
Dependent Claim
23 words
A memory cell array according to claim 1 wherein said conductors are buried under a relatively thick insulating oxide region on said face.
References Cited (Backward Citations)
US4151537A
Cited
US4377818A
Cited
US4455568A
Cited
US4663645A
Cited
US4652897A
Cited
US4698787A
Cited
US4763177A
Cited
US4597060A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-10 | 1994-12-10 | 1995-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-10 | 1998-12-10 | 1999-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-10 | 2002-12-10 | 2003-06-11 | $7700.00 | Window Closed / Lapsed |