Nonvolatile semiconductor memory device of shared contact scheme not having inclined wiring

Claim 2

A read-only semiconductor memory device comprising: a semiconductor substrate; and a plurality of memory elements arranged in a principal surface of said semiconductor substrate in a matrix to form MOS transistors each having a first electrode, a second electrode and a control electrode controlling a channel formed between the first and second electrodes; said plurality of memory elements each comprising: first and second electrode regions respectively formed in said principal surface so as to respectively constitute the first and second electrodes; insulative layers formed on the principal surface; and a control electrode layer formed via said insulative layers on said principal surface to constitute the control electrode; said control electrode layer being commonly connected to said plurality of memory elements in a first direction of the matrix; said first electrode regions being arranged such that any adjacent two in a second direction, substantially perpendicular to the first direction, of said plurality of memory elements electrically share the first electrodes; each of said first electrode regions being interconnected to the first electrode region of one of said plurality of memory elements adjacent thereto in the first direction of the matrix; said second electrode regions being arranged such that any two in the second direction of said plurality of memory elements electrically share the second electrodes; each of said second electrode regions being interconnected to the second electrode region of one of said plurality of memory elements adjacent thereto in the first direction of the matrix; said device further comprising: a plurality of first conductor members each formed on said insulative layers so as to electrically interconnect said first electode regions of ones of said plurality of memory elements in the second direction of the matrix; and a plurality of second conductor members each formed on said insulative layers so as to electrically interconnected said second electode regions of ones of said plurality of memory elements in the second direction of the matrix; boundaries between said control electrode layer and said first and second electrodes being defined in the first direction substantially in parallel thereto.

Claim 3

A memory device in accordance with claim 1, wherein said first and second electrode regions extend in the first direction.

Claim 4

A memory device in accordance with claim 1, wherein each of said memory elements comprises: an additional insulative layer formed on the principal surface and below said control electrode; and a gate electrode layer formed via said additional insulative layer over the principal surface so as to constitute a floating gate electrode of the MOS transistor; whereby said device functions as an EPROM.

Claim 5

A memory device in accordance with claim 1, wherein said first and second electrode regions are respectively source and drain electrodes of the MOS transistors.

Claim 6

A memory device in accordance with claim 1, wherein said substrate is of a p-type material, said first and second electrode regions being of n-type materials.

Claim 7

A memory device in accordance with claim 1, wherein said control electrode layers function as word lines of said memory device, said first and second conductor members functioning as bit lines thereof.

Claim 8

A semiconductor memory device wherein a plurality of MOS transistors are formed in an array of storage cells, each of said plurality of MOS transistors including a floating gate electrode, a control gate electrode, and source and drain regions, comprising: a semiconductor substrate; a plurality of floating gate electrode layers being operative as the floating gate electrodes; a first plurality of insulative layers each surrounding one of said plurality of floating gate electrode layers; said plurality of floating gate electrode layers and said first plurality of insulative layers being disposed on said semiconductor substrate in a matrix formed by columns extending in a first direction and rows extending in a second direction substantially perpendicular to the first direction; a plurality of diffusion regions formed in the matrix in said semiconductor substrate between ones of said floating gate electrode layers, which are adjacent in the first direction, to function as the source and drain regions; corresponding ones of said plurality of diffusion regions between adjacent ones of the columns being extended to be so interconnected to each other that alternate ones of said plurality of diffusion regions in each of the columns are interconnected to corresponding ones of said plurality of diffusion regions in one of the columns which is adjacent thereto, with remaining alternate ones of said plurality of diffusion regions in each of the columns being interconnected to corresponding ones of said plurality of diffusion regions in the other adjacent one of the columns; row conductor layers formed over ones of said plurality of floating gate electrode layers in the form of substantially linear strips extending in the second direction to function as the control electrodes interconnected to each other in the second direction; a second insulative layer formed over said semiconductor substrate and said row conductor layers, and having openings formed therein above contact portions of said diffusion regions; first plurality of column conductor layers formed on said second insulative layer, and each connecting ones of said plurality of diffusion regions, which are included in alternate one of the columns, through the openings with two of said row conductor layers being crossed inbetween; and second plurality of columns conductor layers formed on said second insulative layer, and each connecting ones of said plurality of diffusion regions, which are included in remaining alternate one of the columns, through the openings with two of said row conductor layers being crossed inbetween.

Claim 9

A semiconductor memory device wherein a plurality of MOS transistors are formed in an array of storage cells, each of said plurality of MOS transistors including a floating gate electrode, a control gate electrode, and source and drain regions, comprising: a semiconductor substrate; a plurality of floating gate electrode layers being operative as the floating gate electrodes; a first plurality of insulative layers each surrounding one of said plurality of floating gate electrode layers; said plurality of floating gate electrode layers and said first plurality of insulative layers being disposed on said semiconductor substrate in a matrix formed by columns extending in a first direction and rows extending in a second direction substantially perpendicular to the first direction; a plurality of diffusion regions formed in the matrix in said semiconductor substrate between ones of said floating gate electrode layers, which are adjacent in the first direction, to function as the source and drain regions; corresponding ones of said plurality of diffusion regions between adjacent ones of the columns being extended to be so interconnected to each other that alternate ones of said plurality of diffusion regions in each of the columns are interconnected to corresponding ones of said plurality of diffusion regions in one of the columns which is adjacent thereto, with remaining alternate ones of said plurality of diffusion regions in each of the columns being interconnected to corresponding ones of said plurality of diffusion regions in the other adjacent one of the columns; row conductor layers formed over ones of said plurality of floating gate electrode layers in the form of substantially linear strips extending in the second direction to function as the control electrodes interconnected to each other in the second direction; a second insulative layer formed over said semiconductor substrate and said row conductor layers, and having openings formed therein above contact portions of said diffusion regions; first plurality of column conductor layers formed on said second insulative layer, and each connecting ones of said plurality of diffusion regions, which are included in alternate one of the columns, through the openings with two of said row conductor layers being crossed inbetween; and second plurality of columns conductor layers formed on said second insulative layer, and each connecting ones of said plurality of diffusion regions, which are included in remaining alternate one of the columns, through the openings with two of said row conductor layers being crossed inbetween.

Claim 10

A memory device in accordance with claim 7, wherein boundaries between said floating gate electrode layers and said diffusion regions are defined in the second direction substantially in parallel thereto.

Claim 11

A memory device in accordance with claim 7, wherein said substrate is of a p-type material, said diffusion regions being of n-type materials.

Claim 12

A memory device in accordance with claim 7, wherein said control electrode layers function as word lines of said memory device, said first and second column conductor layers functioning as bit lines thereof.