US4467453A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrically programmable floating gate semiconductor memory device
Assignee: Texas Instruments Inc
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Filing: 1983-02-28
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Granted: 1984-08-21
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Expires: 2003-02-28
Abstract
Abstract An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.
Inventors
- 👤 Te-Long Chiu
- 👤 Jih-Chang Lien
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:40
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
208 words
An electrically programmable, nonvolatile, floating gate, semiconductor memory array comprising: a plurality of MOS transistor devices formed in a face of a semiconductor body each having a source, a drain, a channel, a floating gate, and a control gate, each transistor device having a region in the semiconductor body adjacent the drain doped more heavily than the body, said region not extending the entire length of the channel, the transistor devices being arranged in an array of rows and columns; means for connecting the control gates of all devices in each row together to provide row lines; means connecting the sources of a plurality of said devices together to provide first column lines; means connecting the drains of all devices in each column together to provide second column lines; there being a plurality of second column lines for each first column line; means for selecting one of the row lines and applying a high voltage to it while applying a low voltage to the remaining row lines; means for selecting one of the second column lines and applying a high voltage to it while applying a low voltage to all of the other second column lines; means for applying low voltage to all of the first column lines.
Claim 2
Dependent Claim
208 words
An electrically programmable, nonvolatile, floating gate, semiconductor memory array comprising: a plurality of MOS transistor devices formed in a face of a semiconductor body each having a source, a drain, a channel, a floating gate, and a control gate, each transistor device having a region in the semiconductor body adjacent the drain doped more heavily than the body, said region not extending the entire length of the channel, the transistor devices being arranged in an array of rows and columns; means for connecting the control gates of all devices in each row together to provide row lines; means connecting the sources of a plurality of said devices together to provide first column lines; means connecting the drains of all devices in each column together to provide second column lines; there being a plurality of second column lines for each first column line; means for selecting one of the row lines and applying a high voltage to it while applying a low voltage to the remaining row lines; means for selecting one of the second column lines and applying a high voltage to it while applying a low voltage to all of the other second column lines; means for applying low voltage to all of the first column lines.
Claim 3
Dependent Claim
28 words
A memory array according to claim 1 wherein the transistor devices are N-channel, said region is P type, and the floating gate and control gate are polycrystalline silicon.
Claim 4
Dependent Claim
54 words
A memory array according to claim 2 wherein means are provided for reading data from the array by applying a voltage less than said high voltage to a selected one of the row lines, grounding the first column lines, and detecting the impedence between a selected one of the second column lines and ground.
References Cited (Backward Citations)
US4184207A
Cited
US4222063A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-21 | 1988-02-20 | 1988-08-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-21 | 1992-02-20 | 1992-08-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-21 | 1996-02-20 | 1996-08-21 | $7700.00 | Window Closed / Lapsed |