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EP0105802A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Programmable read only memory

Assignee: Fairchild Semiconductor Corp
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Filing: 1983-09-29
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Granted: —
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Expires: 2003-09-29
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Abstract

Abstract Unique EPROM and EEPROM devices are provided with a composite dielectric layer between the control gate and the floating gate which is sufficiently thick to provide electrical and physical integrity but also has a high equivalent dielectric constant. The use of the composite dielectric layer alleviates certain problems experienced in the prior art EPROM and EEPROM devices which utilize a polycrystalline silicon floating gate and a polycrystalline silicon control gate separated by an Si0 2 dielectric layer, such as the problems of sharp silicon points polysilicon grain growth causing low dielectric breakdown strength. In contrast to the prior art, a composite dielectric layer serves as a partially relaxable dielectric between the control gate and the floating gate of an EEPROM or an EPROM. The composite dielectric layer provides high capacitance between the floating gate and the control gate without the insulative and breakdown problems encountered with prior art thin dielectric layers, with electron injection taking place through the gate oxide between the drain extension and the floating gate, (EEPROM), and between the channel and the floating gate (EPROM). In another embodiment of this invention, the composite dielectric layer is implemented between the drain extension (EEPROM) or the channel (EPROM) and the floating gate and serves as the tunnel oxide.

Inventors

  • 👤 Ning Hsieh

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 19:40
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342; H10B; H10B69/00; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/682; H10D30/683; H10D64/01346; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 124 words
A Programmable Read Only Memory structure, comprising a plurality of cells each including : a semi conductor substrate; a source (83, 93) formed within said substrate; a drain (84,94) formed within said substrate; a channel region formed within said substrate between said source and said drain; a floating gate (81, 91) located above said channel and spaced apart from said channel by a gate dielectric (87a, 97); and a control gate (80, 90) located above and separated from said floating gate (81, 91) by a dielectric (86, 96); characterized in that at least one of said dielectrics is a partially relaxable dielectric wherein the charge stored on said floating gate is altered by the transfer of charge from said floating gate through said dielectric.
Claim 2
Dependent Claim 124 words
A Programmable Read Only Memory structure, comprising a plurality of cells each including : a semi conductor substrate; a source (83, 93) formed within said substrate; a drain (84,94) formed within said substrate; a channel region formed within said substrate between said source and said drain; a floating gate (81, 91) located above said channel and spaced apart from said channel by a gate dielectric (87a, 97); and a control gate (80, 90) located above and separated from said floating gate (81, 91) by a dielectric (86, 96); characterized in that at least one of said dielectrics is a partially relaxable dielectric wherein the charge stored on said floating gate is altered by the transfer of charge from said floating gate through said dielectric.
Claim 3
Dependent Claim 52 words
The structure as in Claim 1, characterized in that said partially relaxable dielectric comprises: a first layer (86a) of a silicon-rich oxide of silicon; a second layer (86c) of a silicon-rich oxide of silicon; and a third layer (86b) of an oxide of silicon located between said first and said second layers.
Claim 4
Dependent Claim 26 words
The structure as in Claim 2, characterized in that said first and said second layers (86a, 86c) comprise approximately 40 to 65 % atomic percent silicon.
Claim 5
Dependent Claim 32 words
The structure as in Claim 2 or 3, characterized in that said first and said second layers (86a, 86c) each 0 have thickness within the range of approximately 150A to 0 500A.
Claim 6
Dependent Claim 31 words
The structure as in any one of Claims 2 to 4, characterized in that said third layer (86b) has a thickness 0 0 within the range of approximately 100A to 300A.
Claim 7
Dependent Claim 48 words
The structure as in Claim 1, characterized in that said partially relaxable dielectric comprises: a first layer (86a) of silicon-rich silicon nitride; a second layer (86c) of silicon-rich silicon nitride; and a third layer (86b) of an oxide of silicon located between said first and said second layers.
Claim 8
Dependent Claim 46 words
The structure as in Claim 1, characterized in that said partially relaxable dielectric comprises: a first layer (86a) of silicon-rich silicon nitride; a second layer (86c) of silicon-rich silicon nitride; and a third layer (86b) of silicon nitride located between said first and said second layers.
Claim 9
Dependent Claim 68 words
The structure as in any one of Claims 2 to 7, characterized in that said partially relaxable dielectric has a relaxation time within the range of approximately 10 to 100 microseconds, where said relaxation time is defined as the time required between the application of a voltage across said first and second layers and the time when approximately 95 % of said voltage appears across said third layer.
Claim 10
Dependent Claim 50 words
The structure as in any one of Claims 1 to 8, characterized in that said gate dielectric includes a tunnel portion (85) having a thickness less than the thickness of the remainder of said gate dielectric, said tunnel portion (85) and said gate dielectric (86) comprising said partially relaxable dielectric.
Claim 11
Dependent Claim 30 words
The structure of any one of Claims 1 to 8, characterized in that said charge on said floating gate (91) is removed by exposing said floating gate to ultraviolet light.

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