US4829351A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Polysilicon pattern for a floating gate memory
Assignee: NXP USA Inc
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Filing: 1987-03-16
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Granted: 1989-05-09
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Expires: 2007-03-16
Abstract
Abstract An integrated circuit floating gate memory is formed using two layers of polysilicon. The first layer of polysilicon is patterned twice, once before the second polysilicon layer is deposited, and again as part of the etch of the second layer of polysilicon. Stringers of the second layer of polysilicon can form along the edge of the first etch of the first layer of polysilicon. The first etch of the first layer of polysilicon is patterned so that even if these stringers are subsequently formed, there is no harm.
Inventors
- 👤 Bruce E. Engles
- 👤 Gianfranco Gerosa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:22
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10B; H10B41/00; H10B41/30; H10B69/00; Y; Y10; Y10T; Y10T428/00; Y10T428/12; Y10T428/12493; Y10T428/12528
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
260 words
A patterned layer of first polysilicon for use in making an integrated circuit memory in a substrate having an array of floating gate transistors, each floating gate transistor having a control gate formed in a layer of second polysilicon which is formed after the patterned layer of first polysilicon is formed and being a portion of a respective word line, a floating gate formed from a portion of said patterned layer of first polysilicon, a drain formed in the substrate and connected to a respective bit line at a respective bit line connecting node formed in the substrate, and a source connected to a respective common source line formed in the substrate, said word lines running generally in a first direction, said bit lines overlying the bit line connecting nodes and running generally in a second direction which is generally orthogonal to the first direction, said common source lines running generally in the first direction; said patterned layer of first polysilicon comprising: a plurality of strips of first polysilicon running generally in the second direction, each of said strips of first polysilicon overlying a single line of respective bit line connecting nodes and being adjaceet to at least one other strip; and a plurality of first bridges of first polysilicon running generally in the first direction and connecting the adjacent strips of first polysilicon, each of said first bridges aligned with two of the bit line connecting nodes, one of said two bit line connecting nodes being from each of the adjacent strips to which the particular bridge is connected.
Claim 2
Dependent Claim
260 words
A patterned layer of first polysilicon for use in making an integrated circuit memory in a substrate having an array of floating gate transistors, each floating gate transistor having a control gate formed in a layer of second polysilicon which is formed after the patterned layer of first polysilicon is formed and being a portion of a respective word line, a floating gate formed from a portion of said patterned layer of first polysilicon, a drain formed in the substrate and connected to a respective bit line at a respective bit line connecting node formed in the substrate, and a source connected to a respective common source line formed in the substrate, said word lines running generally in a first direction, said bit lines overlying the bit line connecting nodes and running generally in a second direction which is generally orthogonal to the first direction, said common source lines running generally in the first direction; said patterned layer of first polysilicon comprising: a plurality of strips of first polysilicon running generally in the second direction, each of said strips of first polysilicon overlying a single line of respective bit line connecting nodes and being adjaceet to at least one other strip; and a plurality of first bridges of first polysilicon running generally in the first direction and connecting the adjacent strips of first polysilicon, each of said first bridges aligned with two of the bit line connecting nodes, one of said two bit line connecting nodes being from each of the adjacent strips to which the particular bridge is connected.
Claim 3
Dependent Claim
33 words
The patterned layer of first polysilicon of claim 1 further comprising: a plurality of second bridges of first polysilicon connected between the adjacent strips of first polysilicon and overlying the common source lines.
Claim 4
Dependent Claim
223 words
A patterned layer of first polysilicon for use in making an integrated circuit memory in a substrate having an array of floating gate transistors, each floating gate transistor having a control gate formed in a layer of second polysilicon which is formed after the patterned layer of first polysilicon is formed and being a portion of a respective word line, a floating gate formed from a portion of said patterned layer of first polysilicon, a drain formed in the substrate and connected to a respective bit line at a respective bit line connecting node formed in the substrate, and a source connected to a respective common source line formed in the substrate, said word lines running generally in a first direction, said bit lines overlying the bit line connecting nodes and running generally in a second direction which is generally orthogonal to the first direction, said common source lines running generally in the first direction; said patterned layer of first polysilicon comprising: a plurality of strips of first polysilicon running generally in the second direction, each of said strips of first polysilicon overlying a single line of respective bit line connecting nodes and being adjacent to at least one other strip; and a plurality of bridges of first polysilicon connected between the strips of adjacent polysilicon bridges and overlying the common source lines.
Claim 5
Dependent Claim
223 words
A patterned layer of first polysilicon for use in making an integrated circuit memory in a substrate having an array of floating gate transistors, each floating gate transistor having a control gate formed in a layer of second polysilicon which is formed after the patterned layer of first polysilicon is formed and being a portion of a respective word line, a floating gate formed from a portion of said patterned layer of first polysilicon, a drain formed in the substrate and connected to a respective bit line at a respective bit line connecting node formed in the substrate, and a source connected to a respective common source line formed in the substrate, said word lines running generally in a first direction, said bit lines overlying the bit line connecting nodes and running generally in a second direction which is generally orthogonal to the first direction, said common source lines running generally in the first direction; said patterned layer of first polysilicon comprising: a plurality of strips of first polysilicon running generally in the second direction, each of said strips of first polysilicon overlying a single line of respective bit line connecting nodes and being adjacent to at least one other strip; and a plurality of bridges of first polysilicon connected between the strips of adjacent polysilicon bridges and overlying the common source lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-08 | 1992-11-07 | 1993-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-08 | 1996-11-07 | 1997-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-08 | 2000-11-07 | 2001-05-09 | $7700.00 | Window Closed / Lapsed |