US4855800A
Expired / Lapsed
US
⏱️ 0.0 years remaining
EPROM with increased floating gate/control gate coupling
Assignee: Texas Instruments Inc
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Filing: 1987-09-11
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Granted: 1989-08-08
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Expires: 2007-09-11
Abstract
Abstract Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between the bit lines (14). An insulated floating gate conductor (18) and an insulated control gate conductor (23) are formed over the wafer and patterned to extend over the dielectric-filled trenches (24). The enhanced coupling efficiency between the control gate (23) and the floating gate (18) enhances the programmability of the memory cells.
Inventors
- 👤 Agerico L. Esquivel
- 👤 Robert Groover, III
- 👤 Howard L. Tigelaar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:24
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B69/00; H10D; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/014; H10W10/10; H10W10/13; H10W10/17
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
129 words
A non-volatile memory cell array, comprising: a semiconductor body; a plurality of bit line diffusions extending along a surface of said semiconductor body; a plurality of word lines crossing said bit line diffusions; a plurality of floating gates, each floating gate underlying one of said word lines at a location between a pair of said bit line diffusions, each said floating gate defining a transistor channel location substantially thereunder; and a plurality of trenches in said semiconductor body, each of said trenches for isolating adjacent ones of said channel locations in the direction said bit line diffusions extend; wherein said word lines and said floating gates each include a first extension overlying an adjacent trench, each first floating gate extension underlying a first extension of its overlying word line.
Claim 2
Dependent Claim
129 words
A non-volatile memory cell array, comprising: a semiconductor body; a plurality of bit line diffusions extending along a surface of said semiconductor body; a plurality of word lines crossing said bit line diffusions; a plurality of floating gates, each floating gate underlying one of said word lines at a location between a pair of said bit line diffusions, each said floating gate defining a transistor channel location substantially thereunder; and a plurality of trenches in said semiconductor body, each of said trenches for isolating adjacent ones of said channel locations in the direction said bit line diffusions extend; wherein said word lines and said floating gates each include a first extension overlying an adjacent trench, each first floating gate extension underlying a first extension of its overlying word line.
Claim 3
Dependent Claim
12 words
The device of claim 1, wherein said floating gates comprise polycrystalline silicon.
Claim 4
Dependent Claim
12 words
The device of claim 1, wherein said word lines comprise polycrystalline silicon.
Claim 5
Dependent Claim
14 words
The device of claim 1, wherein said trenches are filled with a dielectric material.
Claim 6
Dependent Claim
31 words
The device of claim 1, wherein said transistor channel locations define respective floating gate transistors having portions of respective ones of said bit line diffusions as respective source and drain electrodes.
Claim 7
Dependent Claim
31 words
The device of claim 1, wherein said floating gates each further include a second extension overlying the adjacent trench on the opposite side of said channel region from said first extension.
Claim 8
Dependent Claim
31 words
The device of claim 1, further comprising: bit line insulator strips, overlying said bit line diffusions; wherein said floating gates each further include extensions over the adjacent bit line insulator strips.
Claim 9
Dependent Claim
150 words
A non-volatile memory cell array, comprising: a semiconductor body; a plurality of substantially parallel bit line insulator strips extending along a surface of said semiconductor body; a plurality of bit line diffusions, each underlying one of said bit line insulator strips; a plurality of word lines crossing said bit line diffusions; a plurality of floating gates, each floating gate underlying one of said word lines at a location between a pair of said bit line diffusions, each said floating gate defining a transistor channel location substantially thereunder; and a plurality of dielectric-filled trenches in said semiconductor body, each of said trenches for isolating adjacent ones of said channel locations in the direction said bit line insulator strips extend; wherein said word lines and said floating gates each include a first extension overlying an adjacent dielectric-filled trench, each first floating gate extension underlying a first extension of its overlying word line
Claim 10
Dependent Claim
150 words
A non-volatile memory cell array, comprising: a semiconductor body; a plurality of substantially parallel bit line insulator strips extending along a surface of said semiconductor body; a plurality of bit line diffusions, each underlying one of said bit line insulator strips; a plurality of word lines crossing said bit line diffusions; a plurality of floating gates, each floating gate underlying one of said word lines at a location between a pair of said bit line diffusions, each said floating gate defining a transistor channel location substantially thereunder; and a plurality of dielectric-filled trenches in said semiconductor body, each of said trenches for isolating adjacent ones of said channel locations in the direction said bit line insulator strips extend; wherein said word lines and said floating gates each include a first extension overlying an adjacent dielectric-filled trench, each first floating gate extension underlying a first extension of its overlying word line
Claim 11
Dependent Claim
12 words
The device of claim 8, wherein said floating gates comprise polycrystalline silicon.
Claim 12
Dependent Claim
12 words
The device of claim 8, wherein said word lines comprise polycrystalline silicon.
Claim 13
Dependent Claim
16 words
The device of claim 8, wherein said trenches are filled with a silicon oxide dielectric material.
Claim 14
Dependent Claim
31 words
The device of claim 8, wherein said transistor channel locations define a floating gate transistor having portions of respective ones of said bit line diffusions as respective source and drain electrodes.
Claim 15
Dependent Claim
31 words
The device of claim 8, wherein said floating gates each further include a second extension overlying the adjacent trench on the opposite side of said channel region from said first extension.
Claim 16
Dependent Claim
20 words
The device of claim 8 wherein said floating gates each further include extensions over the adjacent bit line insulator strips.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-07 | 1993-02-06 | 1993-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-07 | 1997-02-06 | 1997-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-07 | 2001-02-06 | 2001-08-08 | $7700.00 | Window Closed / Lapsed |