Patent US4829017A successfully refreshed from Google Patents.
US4829017A
Expired / Lapsed
US
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Method for lubricating a high capacity dram cell
Assignee: Texas Instruments Inc
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Filing: 1986-09-25
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Granted: 1989-05-09
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Expires: 2006-09-25
Abstract
Abstract A dynamic random access memory cell (14) is disclosed which is characterized by a high capacity storage element and small lateral wafer area. The cell (14) is constructed with a word line (40) overlying a split bit line (48, 50), with an underlying transistor 30, and yet thereunder a high capacitance capacitor (34). The word line (40) includes a member (42) isolated from the bit line (36) and formed therethrough to provide the transistor gate conductor. The transistor gate insulator (44) covers the gate conductor (42), and is encircled by a transistor semiconductor region (46) forming a vertical transistor conduction channel. The split bit line elements (48, 50) are in electrical contact with an underlying transistor drain region (126). The transistor conduction channel (46) is also in contact with an underlying transistor source region forming one plate (52) of the capacitor (34). The capacitor plate (52) is a core which is enclosed annularly by dielectric isolation (54). Another semiconductor capacitor plate (56) encircles the dielectric isolation (54).
Inventors
- 👤 Satwinder S. Malhi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:24
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/39; H10B12/395; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0383
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
192 words
A method of fabricating a semiconductor memory cell on a substrate, comprising the steps of: forming a layer of a semiconductor material of a first conductivity type on said substrate; forming an annular trench partially into said semiconductor material; forming a diffusion barrier on the top side walls of the said trench; diffusing an impurity of a second conductivity type into the exposed side walls of the said trench to thereby define a capacitor core plate in said semiconductor material; forming said trench deeper into the substrate; forming a thin insulation layer on the side walls of the trench to thereby form a capacitor dielectric; filling said trench with a semiconductor material of said first conductivity type to thereby form an outer capacitor plate; forming a cavity in said semiconductor material of said first conductivity type in a region overlying said capacitor core plate; forming a thin insulating layer on the sidewalls and the bottom of said cavity to thereby define a gate insulator; forming a semiconductor drain region in said semiconductor material around said gate insulator on an upper part thereof; and filling said cavity to provide a transistor gate conductor.
Claim 2
Independent Claim
192 words
A method of fabricating a semiconductor memory cell on a substrate, comprising the steps of: forming a layer of a semiconductor material of a first conductivity type on said substrate; forming an annular trench partially into said semiconductor material; forming a diffusion barrier on the top side walls of the said trench; diffusing an impurity of a second conductivity type into the exposed side walls of the said trench to thereby define a capacitor core plate in said semiconductor material; forming said trench deeper into the substrate; forming a thin insulation layer on the side walls of the trench to thereby form a capacitor dielectric; filling said trench with a semiconductor material of said first conductivity type to thereby form an outer capacitor plate; forming a cavity in said semiconductor material of said first conductivity type in a region overlying said capacitor core plate; forming a thin insulating layer on the sidewalls and the bottom of said cavity to thereby define a gate insulator; forming a semiconductor drain region in said semiconductor material around said gate insulator on an upper part thereof; and filling said cavity to provide a transistor gate conductor.
Claim 3
Dependent Claim
37 words
The method of claim 1 further including forming a doped semiconductor bit line overlying said transistor, and forming said source by driving the impurities of said bit line into the semiconductor material overlying said capacitor core plate.
Claim 4
Dependent Claim
26 words
The method of claim 1 further including forming a word line overlying line and insulated therefrom by insulation which is formed continuous with said gate insulator.
Claim 5
Dependent Claim
32 words
The method of claim 3 wherein said bit line has formed therein an opening in vertical registry with said cavity and said word line is formed through said opening into said cavity.
Claim 6
Dependent Claim
32 words
The method of claim 1 wherein said substrate and said semiconductor material are formed of the same conductivity type so that said outer capacitor plate is in electrical continuity with said substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-08 | 1992-11-07 | 1993-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-08 | 1996-11-07 | 1997-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-08 | 2000-11-07 | 2001-05-09 | $7700.00 | Window Closed / Lapsed |