EP0088451A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory
Assignee: Hitachi Ltd
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Filing: 1983-03-10
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Granted: —
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Expires: 2003-03-10
Abstract
Abstract A semiconductor memory wherein a part of each capacitor (8, 12, 10) is formed on side walls of an island region surrounded with a recess (17) formed in a semiconductor substrate (10), and the island region and other regions are electrically isolated by the recess.
Inventors
- 👤 Hideo Sunami
- 👤 Tokuo Kure
- 👤 Yoshifumi Kawamoto
- 👤 Masao Tamura
- 👤 Masanobu Miyao
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 17:46
CPC Classifications
H; H10; H10B; H10B12/00; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; H10B12/30; H10B12/39; H10B12/395; H10P; H10P76/00; H10P76/40; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
81 words
A semiconductor memory comprising capacitors (8, 12, 10) which are information storage portions, and insulated-gate field effect transistors (4, 15) which read out signal charges in said information storage portions, a part of each capacitors (8, 12, 10) being formed on side walls of an island region which is surrounded with a recess (17) provided in a surface region of a semiconductor substrate (10), and which is electrically isolated from other regions of said semiconductor substrate (10) by said recess (17).
Claim 2
Dependent Claim
81 words
A semiconductor memory comprising capacitors (8, 12, 10) which are information storage portions, and insulated-gate field effect transistors (4, 15) which read out signal charges in said information storage portions, a part of each capacitors (8, 12, 10) being formed on side walls of an island region which is surrounded with a recess (17) provided in a surface region of a semiconductor substrate (10), and which is electrically isolated from other regions of said semiconductor substrate (10) by said recess (17).
Claim 3
Dependent Claim
26 words
The semiconductor memory of claim 1, wherein each said insulated-gate field effect transistor (4, 15) is formed in a surface region of said semiconductor substrate (10).
Claim 4
Dependent Claim
40 words
The semiconductor memory of claim 1 or 2, wherein a heavily-doped region (20, 25) having the same conductivity type as that of said semiconductor substrate (10) is formed under said recess (17) and/or in a part of the side walls.
Claim 5
Dependent Claim
42 words
The semiconductor memory of any of claims 1 to 3, wherein a heavily-doped region (151...153) possessed by said insulated-gate field effect transistor is formed within a heavily-doped isolation well (21) having the same conductivity type as that of said semiconductor substrate (10).
Claim 6
Dependent Claim
32 words
The semiconductor memory of any of claims 1 to 4, wherein said capacitor comprises an insulating film (12) and a plate electrode (8) which are stacked and formed on the side walls.
Claim 7
Dependent Claim
23 words
The semiconductor memory of any of claims 1 to 5, wherein said capacitor includes a p-n junction capacitor formed on the side walls.
Claim 8
Dependent Claim
43 words
The semiconductor memory of any of claims 1 to 6, wherein said insulated-gate field effect transistor (151... 153, 281, 282) is formed in a single-crystal semiconductor film which is stacked and formed on an insulating film (13) deposited on said semiconductor substrate (10).
References Cited (Backward Citations)
US4151610A
Cited
WO1981003241A1
Cited
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