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JPS6136965A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory device

Assignee: Toshiba Corp
•
Filing: 1984-07-30
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Granted: —
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Expires: 2004-07-30
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Abstract

Abstract PURPOSE:To eliminate the leakage of charges to a substrate and a malfunction resulting from alpha-rays, to enable correct operation by increasing the quantity of charges stored and to lengthen a memory holding time by forming three layers constituting a capacitor cell. CONSTITUTION:A groove 2 is dug to a P type semiconductor substrate 1, and a P<+> diffusion layer 10 is shaped onto the inner surface of the groove. An insulating layer 4 consisting of SiO2 on the inside of the diffusion layer 10 and a polysilicon layer 11 on the inside of the layer 4 are formed. An insulating layer 4 on the inside of the layer 11 and a polysilicon layer 12 on the inside of the layer 4 are shaped. An N channel MOS transistor 6 for taking in and out charges to and from the capacitor cell is formed. According to the constitution, a capacitor element is connected in parallel, thus doubling the quantity of charges stored. Charges are stored in the layer 11 through the transistor 6, thus resulting in no leakage to the substrate 1, then preventing the effect of electrons generated in the substrate 1 by alpha-rays.

Inventors

  • 👤 Yukimasa Uchida
  • 👤 内田 幸正
  • 👤 Toru Kimura
  • 👤 亨 木村

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 01:06
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS583260A Cited
JPS58213460A Cited

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