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US6754108B2
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DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
Assignee: Micron Technology Inc
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Filing: 2001-08-30
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Granted: 2004-06-22
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Expires: 2021-08-30
Abstract
Abstract Structures and methods for memory cells having a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A storage capacitor is coupled to one of the first and the second source/drain regions. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The memory cell is adapted to operate in a first and a second mode of operation. The first mode of operation is a dynamic mode of operation and the second mode of operation is a repressed memory mode of operation.
Inventors
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:07
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10D30/6891; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681
Claims Analysis
Total Claims: 75
Claim 1
Independent Claim
91 words
A memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a storage capacitor coupled to one of the first and the second source/drain regions; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate, wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator; and wherein the memory cell is adapted to operate in a first and a second mode of operation.
Claim 2
Dependent Claim
91 words
A memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a storage capacitor coupled to one of the first and the second source/drain regions; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate, wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator; and wherein the memory cell is adapted to operate in a first and a second mode of operation.
Claim 3
Dependent Claim
19 words
The memory cell of claim 1 , wherein the first mode of operation is a dynamic mode of operation.
Claim 4
Dependent Claim
20 words
The memory cell of claim 1 , wherein the second mode of operation is a repressed memory mode of operation.
Claim 5
Dependent Claim
36 words
The memory cell of claim 1 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of lead oxide (PbO) and aluminum oxide (Al 2 O 3 ).
Claim 6
Dependent Claim
19 words
The memory cell of claim 1 , wherein the low tunnel barrier intergate insulator includes a transition metal oxide.
Claim 7
Dependent Claim
36 words
The memory cell of claim 5 , wherein the transition metal oxide is selected from the group consisting of Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 .
Claim 8
Dependent Claim
20 words
The memory cell of claim 1 , wherein the low tunnel barrier intergate insulator includes a Perovskite oxide tunnel barrier.
Claim 9
Dependent Claim
31 words
The memory cell of claim 1 , wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 10
Dependent Claim
31 words
The memory cell of claim 8 , wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 11
Dependent Claim
15 words
The memory cell of claim 1 , wherein the channel region includes an n-type channel.
Claim 12
Dependent Claim
136 words
A memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a storage capacitor coupled to the second source/drain region; a floating gate opposing the channel region and separated therefrom by a gate oxide; a vertical control gate opposing the floating gate, wherein the vertical control gate is separated from the floating gate by a low tunnel barrier intergate insulator; and wherein the memory cell is controllable to access a first charge representing a data value from the storage capacitor in a first mode of operation and a second charge representing a data value from the floating gate in a second mode of operation, wherein the first charge is accessible without affecting the second charge and the second charge is accessible without affecting the first charge.
Claim 13
Dependent Claim
136 words
A memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a storage capacitor coupled to the second source/drain region; a floating gate opposing the channel region and separated therefrom by a gate oxide; a vertical control gate opposing the floating gate, wherein the vertical control gate is separated from the floating gate by a low tunnel barrier intergate insulator; and wherein the memory cell is controllable to access a first charge representing a data value from the storage capacitor in a first mode of operation and a second charge representing a data value from the floating gate in a second mode of operation, wherein the first charge is accessible without affecting the second charge and the second charge is accessible without affecting the first charge.
Claim 14
Dependent Claim
48 words
The memory cell of claim 11 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 .
Claim 15
Dependent Claim
31 words
The memory cell of claim 11 , wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 16
Dependent Claim
32 words
The memory cell of claim 13 , wherein the vertical control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 17
Dependent Claim
23 words
The memory cell of claim 11 , wherein the floating gate includes a horizontally oriented floating gate formed alongside of the body region.
Claim 18
Dependent Claim
114 words
A memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a storage capacitor coupled to one of the first and the second source/drain regions; a polysilicon floating gate opposing the channel region and separated therefrom by a gate oxide; a first metal layer formed on the polysilicon floating gate; a metal oxide intergate insulator formed on the metal layer; a second metal layer formed on the metal oxide intergate insulator; an edge defined polysilicon control gate formed on the second metal layer; and wherein the storage capacitor is adapted to store volatile data and the floating gate is adapted to store non-volatile data.
Claim 19
Dependent Claim
114 words
A memory cell, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a storage capacitor coupled to one of the first and the second source/drain regions; a polysilicon floating gate opposing the channel region and separated therefrom by a gate oxide; a first metal layer formed on the polysilicon floating gate; a metal oxide intergate insulator formed on the metal layer; a second metal layer formed on the metal oxide intergate insulator; an edge defined polysilicon control gate formed on the second metal layer; and wherein the storage capacitor is adapted to store volatile data and the floating gate is adapted to store non-volatile data.
Claim 20
Dependent Claim
26 words
The memory cell of claim 16 , wherein first and the second metal layers are lead and the metal oxide intergate insulator is lead oxide (PbO).
Claim 21
Dependent Claim
30 words
The memory cell of claim 16 , wherein the first and second metal layer are aluminum and the metal oxide intergate insulator is aluminum oxide (Al 2 O 3 ).
Claim 22
Dependent Claim
32 words
The memory cell of claim 16 , wherein the first and the second metal layers include transition metal layers and the metal oxide intergate insulator includes a transition metal oxide intergate insulator.
Claim 23
Dependent Claim
36 words
The memory cell of claim 19 , wherein the transition metal oxide is selected from the group consisting of Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 .
Claim 24
Dependent Claim
19 words
The memory cell of claim 19 , wherein the metal oxide intergate insulator includes a Perovskite oxide intergate insulator.
Claim 25
Dependent Claim
135 words
A memory array, comprising: a number of memory cells, wherein each memory cell includes: a first source/drain region and a second source/drain region separated by a channel region; a storage capacitor coupled to the second source/drain region; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate, wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator; and wherein the memory cell is adapted to operate in a first and a second mode of operation; a number of bitlines coupled to the first source/drain regions along a first selected direction in the flash memory array; and a number of control gate lines coupled to the control gates along a second selected direction in the flash memory array.
Claim 26
Dependent Claim
135 words
A memory array, comprising: a number of memory cells, wherein each memory cell includes: a first source/drain region and a second source/drain region separated by a channel region; a storage capacitor coupled to the second source/drain region; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate, wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator; and wherein the memory cell is adapted to operate in a first and a second mode of operation; a number of bitlines coupled to the first source/drain regions along a first selected direction in the flash memory array; and a number of control gate lines coupled to the control gates along a second selected direction in the flash memory array.
Claim 27
Dependent Claim
19 words
The memory array of claim 22 , wherein the first mode of operation is a dynamic mode of operation.
Claim 28
Dependent Claim
20 words
The memory array of claim 23 , wherein the second mode of operation is a repressed memory mode of operation.
Claim 29
Dependent Claim
48 words
The memory array of claim 22 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 .
Claim 30
Dependent Claim
31 words
The memory array of claim 22 , wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 31
Dependent Claim
31 words
The memory array of claim 26 , wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 32
Dependent Claim
223 words
An array of memory cells, comprising: a number of access transistors, wherein each access transistor includes a first source/drain region and a second source/drain region separated by a body region having a channel region in a substrate; a number of storage capacitors coupled to the second source/drain regions; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried bitlines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator; and wherein each memory cell in the array of memory cells is controllable to access a first charge representing a data value from the storage capacitor in a first mode of operation and a second charge representing a data value from the floating gate in a second mode of operation, wherein the first charge is accessible without affecting the second charge and the second charge is accessible without affecting the first charge.
Claim 33
Dependent Claim
223 words
An array of memory cells, comprising: a number of access transistors, wherein each access transistor includes a first source/drain region and a second source/drain region separated by a body region having a channel region in a substrate; a number of storage capacitors coupled to the second source/drain regions; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried bitlines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator; and wherein each memory cell in the array of memory cells is controllable to access a first charge representing a data value from the storage capacitor in a first mode of operation and a second charge representing a data value from the floating gate in a second mode of operation, wherein the first charge is accessible without affecting the second charge and the second charge is accessible without affecting the first charge.
Claim 34
Dependent Claim
50 words
The array of memory cells of claim 28 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 .
Claim 35
Dependent Claim
33 words
The array of memory cells of claim 28 , wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 36
Dependent Claim
33 words
The array of memory cells of claim 28 , wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 37
Dependent Claim
23 words
The array of memory cells of claim 28 , wherein the number of control gate lines are disposed vertically above the floating gates.
Claim 38
Dependent Claim
180 words
An array of memory cells, comprising: a number of access transistors, wherein each access transistor includes a first source/drain region and a second source/drain region separated by a body region having a channel region in a substrate; a number of storage capacitors coupled to the second source/drain regions; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of edge defined control gates opposing the floating gates; a number of buried bitlines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of edge defined control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator; and wherein the number of storage capacitors are adapted to store volatile data and the number of floating gates are adapted to store non-volatile data.
Claim 39
Dependent Claim
180 words
An array of memory cells, comprising: a number of access transistors, wherein each access transistor includes a first source/drain region and a second source/drain region separated by a body region having a channel region in a substrate; a number of storage capacitors coupled to the second source/drain regions; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of edge defined control gates opposing the floating gates; a number of buried bitlines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of edge defined control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator; and wherein the number of storage capacitors are adapted to store volatile data and the number of floating gates are adapted to store non-volatile data.
Claim 40
Dependent Claim
199 words
An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein the memory device includes an array of memory cells, comprising: a number of access transistors, wherein each access transistor includes a first source/drain region and a second source/drain region separated by a body region having a channel region in a substrate; a number of storage capacitors coupled to the second source/drain regions; a number of floating gates opposing the body regions in the number of access transistors and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried bitlines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator; and wherein each memory cell in the array of memory cells is adapted to operate in a dynamic mode of operation and a repressed memory mode of operation.
Claim 41
Dependent Claim
199 words
An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein the memory device includes an array of memory cells, comprising: a number of access transistors, wherein each access transistor includes a first source/drain region and a second source/drain region separated by a body region having a channel region in a substrate; a number of storage capacitors coupled to the second source/drain regions; a number of floating gates opposing the body regions in the number of access transistors and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried bitlines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator; and wherein each memory cell in the array of memory cells is adapted to operate in a dynamic mode of operation and a repressed memory mode of operation.
Claim 42
Dependent Claim
48 words
The electronic system of claim 34 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 .
Claim 43
Dependent Claim
31 words
The electronic system of claim 34 , wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 44
Dependent Claim
31 words
The electronic system of claim 34 , wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 45
Dependent Claim
21 words
The electronic system of claim 34 , wherein the number of control gate lines are disposed vertically above the floating gates.
Claim 46
Dependent Claim
19 words
The electronic system of claim 38 , wherein the number of control gate lines are vertical control gate lines.
Claim 47
Dependent Claim
20 words
The electronic system of claim 38 , wherein the number of control gate lines are edge defined control gate lines.
Claim 48
Independent Claim
100 words
A method of forming a memory cell, comprising: forming a first source/drain region and a second source/drain region separated by a channel region in a substrate; forming a storage capacitor coupled to one of the first and the second source/drain regions; forming a floating gate opposing the channel region and separated therefrom by a gate oxide; forming a control gate opposing the floating gate; forming a low tunnel barrier intergate insulator to separate the control gate from the floating gate such that the memory cell is operable in a dynamic mode of operation and a repressed memory mode of operation.
Claim 49
Independent Claim
100 words
A method of forming a memory cell, comprising: forming a first source/drain region and a second source/drain region separated by a channel region in a substrate; forming a storage capacitor coupled to one of the first and the second source/drain regions; forming a floating gate opposing the channel region and separated therefrom by a gate oxide; forming a control gate opposing the floating gate; forming a low tunnel barrier intergate insulator to separate the control gate from the floating gate such that the memory cell is operable in a dynamic mode of operation and a repressed memory mode of operation.
Claim 50
Dependent Claim
37 words
The method of claim 41 , wherein forming the low tunnel barrier intergate insulator includes forming a metal oxide insulator selected from the group consisting of lead oxide (PbO) and aluminum oxide (Al 2 O 3 ).
Claim 51
Dependent Claim
21 words
The method of claim 41 , wherein forming the low tunnel barrier intergate insulator includes forming a transition metal oxide insulator.
Claim 52
Dependent Claim
43 words
The method of claim 43 , wherein forming the transition metal oxide insulator includes forming the transition metal oxide insulator selected from the group consisting of Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 .
Claim 53
Dependent Claim
32 words
The method of claim 41 , wherein forming the floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 54
Dependent Claim
33 words
The method of claim 41 , wherein forming the control gate includes a forming a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 55
Independent Claim
236 words
A method for forming an array of memory cells, comprising: forming a number of access transistors, wherein forming each access transistor includes forming a first source/drain region and a second source/drain region separated by a body region having a channel region in a substrate; forming a number of storage capacitors coupled to the second source/drain regions; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of buried bitlines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; and forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator such that each memory cell in the array of memory cells is controllable to access a first charge representing a data value from the storage capacitor in a first mode of operation and a second charge representing a data value from the floating gate in a second mode of operation, wherein the first charge is accessible without affecting the second charge and the second charge is accessible without affecting the first charge.
Claim 56
Independent Claim
236 words
A method for forming an array of memory cells, comprising: forming a number of access transistors, wherein forming each access transistor includes forming a first source/drain region and a second source/drain region separated by a body region having a channel region in a substrate; forming a number of storage capacitors coupled to the second source/drain regions; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of buried bitlines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; and forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator such that each memory cell in the array of memory cells is controllable to access a first charge representing a data value from the storage capacitor in a first mode of operation and a second charge representing a data value from the floating gate in a second mode of operation, wherein the first charge is accessible without affecting the second charge and the second charge is accessible without affecting the first charge.
Claim 57
Dependent Claim
49 words
The method of claim 47 , wherein forming the low tunnel barrier intergate insulator includes forming a metal oxide insulator selected from the group consisting of PbO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 .
Claim 58
Dependent Claim
32 words
The method of claim 47 , wherein forming each floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 59
Dependent Claim
32 words
The method of claim 47 , wherein forming each control gate includes forming a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Claim 60
Dependent Claim
34 words
The method of claim 47 , wherein the forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates.
Claim 61
Dependent Claim
30 words
The method of claim 51 , wherein the forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are edge defined.
Claim 62
Independent Claim
156 words
A method for operating a memory cell having repressed memory, comprising: writing to a floating gate of the memory cell using channel hot electron injection, wherein the memory cell includes: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a storage capacitor coupled to one of the first and the second source/drain regions; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator; erasing charge from the floating gate by tunneling electrons off of the floating gate and onto the control gate; and sensing a first charge representing a data value from the storage capacitor in a first mode of operation and a second charge representing a data value from the floating gate in a second mode of operation.
Claim 63
Independent Claim
156 words
A method for operating a memory cell having repressed memory, comprising: writing to a floating gate of the memory cell using channel hot electron injection, wherein the memory cell includes: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a storage capacitor coupled to one of the first and the second source/drain regions; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator; erasing charge from the floating gate by tunneling electrons off of the floating gate and onto the control gate; and sensing a first charge representing a data value from the storage capacitor in a first mode of operation and a second charge representing a data value from the floating gate in a second mode of operation.
Claim 64
Dependent Claim
45 words
The method of claim 53 , wherein erasing charge from the floating gate by tunneling electrons off of the floating gate and onto the control gate further includes: providing a negative voltage to the substrate; and providing a large positive voltage to the control gate.
Claim 65
Dependent Claim
27 words
The method of claim 53 , wherein the method further includes writing to the floating gate by tunneling electrons from the control gate to the floating gate.
Claim 66
Dependent Claim
42 words
The method of claim 55 , wherein writing to the floating gate by tunneling electrons from the control gate to the floating gate further includes: applying a positive voltage to the substrate; and applying a large negative voltage to the control gate.
Claim 67
Dependent Claim
44 words
The method of claim 53 , wherein erasing charge from the floating gate by tunneling electrons off of the floating gate and onto the control gate includes tunneling electrons from the floating gate to the control gate through a low tunnel barrier intergate insulator.
Claim 68
Dependent Claim
71 words
The method of claim 57 , wherein tunneling electrons from the floating gate to the control gate through a low tunnel barrier intergate insulator includes tunneling electrons from the floating gate to the control gate through a low tunnel barrier intergate insulator selected from the group consisting of PbO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , and Nb 2 O 5 .
Claim 69
Dependent Claim
65 words
The method of claim 57 , wherein tunneling electrons from the floating gate to the control gate through a low tunnel barrier intergate insulator includes tunneling electrons from a metal layer formed on the floating gate in contact with the low tunnel barrier intergate insulator to a metal layer formed on the control gate and also in contact with the low tunnel barrier intergate insulator.
Claim 70
Independent Claim
254 words
A method for operating an array of memory cells, comprising: writing to one or more floating gates for a number of memory cells in the array of flash memory cells using channel hot electron injection, the array of flash memory cells includes: a number of access transistors, wherein each access transistor includes a first source/drain region and a second source/drain region separated by a body region having a channel region in a substrate; a number of storage capacitors coupled to the second source/drain regions; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried bitlines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; and a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator; erasing charge from the one or more floating gates by tunneling electrons off of the one or more floating gates and onto the number of control gates; sensing a first charge representing a data value from the storage capacitor in a dynamic mode of operation; and sensing a second charge representing a data value from the floating gate in a repressed memory mode of operation.
Claim 71
Independent Claim
254 words
A method for operating an array of memory cells, comprising: writing to one or more floating gates for a number of memory cells in the array of flash memory cells using channel hot electron injection, the array of flash memory cells includes: a number of access transistors, wherein each access transistor includes a first source/drain region and a second source/drain region separated by a body region having a channel region in a substrate; a number of storage capacitors coupled to the second source/drain regions; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried bitlines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; and a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator; erasing charge from the one or more floating gates by tunneling electrons off of the one or more floating gates and onto the number of control gates; sensing a first charge representing a data value from the storage capacitor in a dynamic mode of operation; and sensing a second charge representing a data value from the floating gate in a repressed memory mode of operation.
Claim 72
Dependent Claim
63 words
The method of claim 60 , wherein erasing charge from the one or more floating gates by tunneling electrons off of the floating gate and onto the number of control gate further includes: providing a negative voltage to a substrate of one or more memory cells; and providing a large positive voltage to the control gate for the one or more memory cells.
Claim 73
Dependent Claim
54 words
The method of claim 61 , wherein the method further includes erasing an entire row of memory cells by providing a negative voltage to all of the substrates along an entire row of memory cells and providing a large positive voltage to all of the control gates along the entire row of memory cells.
Claim 74
Dependent Claim
54 words
The method of claim 61 , wherein the method further includes erasing an entire block of memory cells by providing a negative voltage to all of the substrates along multiple rows of memory cells and providing a large positive voltage to all of the control gates along the multiple rows of non-volatile memory cells.
Claim 75
Dependent Claim
74 words
The method of claim 60 , wherein sensing a first charge representing a data value from the storage capacitor in a dynamic mode of operation and sensing a second charge representing a data value from the floating gate in a repressed memory mode of operation includes controllably sensing each memory cell such that the first charge is accessible without affecting the second charge and the second charge is accessible without affecting the first charge.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-06-22 | 2007-12-22 | 2008-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-06-22 | 2011-12-22 | 2012-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-06-22 | 2015-12-22 | 2016-06-22 | $7700.00 | Window Closed / Lapsed |