Patent US825070A successfully refreshed from Google Patents.
Patent US6714455B2 successfully refreshed from Google Patents.
US6714455B2
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Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
Assignee: MLC Intellectual Property LLC
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Filing: 2002-07-05
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Granted: 2004-03-30
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Expires: 2022-07-05
Abstract
Abstract Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can thus be programmed without reading out its memory state during the programming process, with programming margins being assured by the dependence of the read reference signals on the programming reference signals. Both sets of reference signals may be generated by reference cells which track variations in the operating characteristics of the memory cell with changes in conditions, such as temperature and system voltages, to enhance the reliability of memory programming and readout.
Inventors
- 👤 Gerald J. Banks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:26
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5642; G11C16/30; G11C16/34; G11C16/3436; G11C16/3454; G11C16/3459; G11C16/10; G11C16/14; G11C16/16; G11C16/32; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621; G11C2211/563; G11C2211/5634; G11C2211/564; G11C2211/5642
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
271 words
A non-volatile semiconductor memory device, comprising: a plurality of non-volatile memory cells each of which has a storage structure and an electrically alterable parameter representing data of at least two bits, wherein the eleotrically alterable parameters of the plurality of non-volatile memory cells are shiftable to at least three mutually different first, second and third program states from an erase state; reference, value generating circuitry generating programming reference values for programming the first, second and third program states, and generating read reference values, which are different from the programming reference values, for reading the first, second and third program states; and sensing/program-verifying circuitry receiving the parameter of one non-volatile memory cell, the read reference values and the programing reference values; wherein the sensing/program-verifying circuitry generates data of at least two bits represented by the electrically alterable parameter, verifies whether the electrically alterable parameter is shifted to the parameter indicating a selected one state of the, first, second and third program states, and programs the electrically alterable parameter until it has been verified that the eleetrically alterable parameter has been shifted to the selected one state, wherein the programing reference values are used for verifying whether the electrically alterable parameter is shifted to the first, second or third program state, and the read reference values are used for detecting whether the electrically alterable parameter is near to the first. second or third program state, and wherein the reference value generating circuitry generates the program reference values, and the read reference values such that one of a programming reference value and a read reference value is shifted from and dependent upon the other.
Claim 2
Dependent Claim
271 words
A non-volatile semiconductor memory device, comprising: a plurality of non-volatile memory cells each of which has a storage structure and an electrically alterable parameter representing data of at least two bits, wherein the eleotrically alterable parameters of the plurality of non-volatile memory cells are shiftable to at least three mutually different first, second and third program states from an erase state; reference, value generating circuitry generating programming reference values for programming the first, second and third program states, and generating read reference values, which are different from the programming reference values, for reading the first, second and third program states; and sensing/program-verifying circuitry receiving the parameter of one non-volatile memory cell, the read reference values and the programing reference values; wherein the sensing/program-verifying circuitry generates data of at least two bits represented by the electrically alterable parameter, verifies whether the electrically alterable parameter is shifted to the parameter indicating a selected one state of the, first, second and third program states, and programs the electrically alterable parameter until it has been verified that the eleetrically alterable parameter has been shifted to the selected one state, wherein the programing reference values are used for verifying whether the electrically alterable parameter is shifted to the first, second or third program state, and the read reference values are used for detecting whether the electrically alterable parameter is near to the first. second or third program state, and wherein the reference value generating circuitry generates the program reference values, and the read reference values such that one of a programming reference value and a read reference value is shifted from and dependent upon the other.
Claim 3
Dependent Claim
33 words
A non-volatile semiconductor memory device according to claim 1 , wherein a shift amount of the read reference value from the corresponding programming reference value is dependent upon the corresponding programing reference value.
Claim 4
Dependent Claim
134 words
A non-volatile semiconductor memory device according to claim 1 , wherein the reference value generating circuitry includes: a first reference value generating Circuit which generates first one of said programming reference values and a first one of said read reference values, a second reference value generating circuit which generates a second one of said prograning reference values and a second one of said read reference values, and a third reference value generating circuit which generates a third one of paid programing reference vales and a third one of said read reference values, and wherein each of the first reference value generating circuit, the second reference value generating circuit and the third reference value generating circuit includes an element causing the corresponding read reference value and the corresponding programming reference value to have different values.
Claim 5
Dependent Claim
78 words
A non-volatile semiconductor memory device according to claim 3 , wherein each of the first reference value generating circuit, the second reference value generating circuit and the third reference value generating circuit further includes a reference cell which has substantially the same construction as each of said plurality of memory cells, and the reference cell and the element of each reference value generating circuit cooperate to provide a predetermined difference between the corresponding read and programming reference values.
Claim 6
Dependent Claim
23 words
A non-volatile semiconductor memory device according to claim 1 , wherein each read reference value is dependent upon the corresponding programming reference value.
Claim 7
Dependent Claim
75 words
A non-volatile semiconductor memory device according to claim 1 , wherein a conductivity value of the one non-volatile memory cell is decreased in order of the state indicating the erase state, the first program state, the second program state and the third program state, and wherein the programming states of non-volatile memory cells of one of a byte, a block and a chip level can be shifted to the erase state by an erase operation.
Claim 8
Dependent Claim
38 words
A non-volatile semiconductor memory device according to claim 6 , wherein each of the plurality of non-volatile memory cells has a floating gate to which electrons are capable of being injected from a channel by hot electron injection.
Claim 9
Dependent Claim
37 words
A non-volatile semiconductor memory device according to claim 6 , wherein each of the plurality of non-volatile memory cells has a floating gate to which electrons are capable of being injected from a channel by Fowler-Nordheim tunneling.
Claim 10
Dependent Claim
75 words
A non-volatile semiconductor memory device according to claim 2 , wherein a conductivity value of the one non-volatile memory cell is decreased in order of the state indicating the erase state, the first program state, the second program state and the third program state, and wherein the programming state of non-volatile memory cells of one of a byte, a block and a chip level can be shifted to the erase state by an erase operation.
Claim 11
Dependent Claim
38 words
A non-volatile semiconductor memory device according to claim 9 . wherein each of the plurality of non-volatile memory cells has a floating gate to which electrons are capable of being injected from a channel by hot electron injection.
Claim 12
Dependent Claim
37 words
A non-volatile semiconductor memory device according to claim 9 , wherein each of the plurality of non-volatile memory cells has a floating gate to which electrons are, capable of being injected from a channel by Fowler-Nordheim tunneling.
Claim 13
Dependent Claim
74 words
A non-volatile semiconductor memory device according to claim 3 , wherein a conductivity value of the one non-volatile memory cell is decreased in order of the state indicating the erase state, the first program state, the second program state and the third program state, and wherein conductivity values of non-volatile memory cells of one of a byte, a block and a chip level can be shifted to the erase state, by an erase operation.
Claim 14
Dependent Claim
38 words
A non-volatile semiconductor memory device according to claim 12 , wherein each of the plurality of non-volatile memory cells has a floating gate to which electrons are capable of being injected from a channel by hot electron injection.
Claim 15
Dependent Claim
37 words
A non-volatile semiconductor memory device according to claim 12 , wherein each of the plurality of non-volatile memory cells has a floating gate to which electrons are capable of being injected from a channel by Fowler-Nordheim tunneling.
Claim 16
Dependent Claim
74 words
A non-volatile semiconductor memory device, according to claim 4 , wherein a conductivity value of the one non-volatile memory cell is decreased in order of the state indicating the erase state, the first program state, the second program state and the third program state, and wherein conductivity value of non-volatile memory cells of one of a byte, a block and a chip level can be shifted to the erase state by an erase operation.
Claim 17
Dependent Claim
38 words
A non-volatile semiconductor memory device according to claim 15 , wherein each of the plurality of non-volatile memory cells has a floating gate to which electrons are capable of being injected from a channel by hot electron injection.
Claim 18
Dependent Claim
37 words
A non-volatile semiconductor memory device according to claim 15 , wherein each of the plurality of non-volatile memory cells has a floating gate to which electrons are capable of being injected from a channel by Fowler-Nordheim tunneling.
Claim 19
Dependent Claim
74 words
A non-volatile semiconductor memory device according to claim 5 , wherein a conductivity value of the one non-volatile memory cell is decreased in order of the state indicating the erase state, the first program state, the second program state and the third program state, and wherein conductivity values of non-volatile memory cells of one of a byte, a block and a chip level can be shifted to the erase state by an erase operation.
Claim 20
Dependent Claim
38 words
a non-volatile semiconductor memory device according to claim 18 , wherein each of the plurality of non-volatile memory cells has a floating gate to which electrons are capable of being injected from a channel by hot electron injection.
Claim 21
Dependent Claim
37 words
A non-volatile semiconductor memory device according to claim 18 . wherein each of the plurality of non-volatile memory cells has a floating gate to which electrons are capable of being injected from a channel by Fowler-Nordheim tunneling.
Claim 22
Dependent Claim
31 words
A non-volatile semiconductor memory device according to clam 1 , wherein the first, second and third read reference values are dependent upon the first, second and third programming reference values, respectively.
Claim 23
Dependent Claim
31 words
A non-volatile semiconductor memory device according to clam 1 , wherein the first, second and third read reference values are dependent upon the first, second and third programming reference values, respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-03-30 | 2007-09-29 | 2008-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-03-30 | 2011-09-29 | 2012-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-03-30 | 2015-09-29 | 2016-03-30 | $7700.00 | Window Closed / Lapsed |