Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell

Claim 2

For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, and reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell, wherein the operation for settling the parameter includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programming pulse supplied to the bit line, and wherein the program operation is carried out by variable length programming pulses, the variable length programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first progranmming pulse has a first programming term and the second programming pulse has a second programming term being shorter than the first programming term.

Claim 3

The method of operating the electrically alterable non-volatile multi-level memory according to claim 1, wherein the variable length programming pulses grow progressively shorter as the one non-volatile multi-level memory cell approaches an appropriate voltage threshold.

Claim 4

The method of operating the electrically alterable non-volatile multi-level memory according to claim 1, further comprising, verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the operation for reading the status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, and wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.

Claim 5

The method of operating the electrically alterable non-volatile multi-level memory according to claim 3, wherein the normal read operation is carried out by parallel-comparing the parameter with the plurality of reading reference parameters by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter.

Claim 6

The method of operating the electrically alterable non-volatile multi-level memory according to claim 3, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 7

The method of operating the electrically alterable non-volatile multi-level memory according to claim 4, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 8

The method of operating the electrically alterable non-volatile multi-level memory according to claim 2, further comprising, verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the operation for reading the status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, and wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.

Claim 9

The method of operating the electrically alterable non-volatile multi-level memory according to claim 7, wherein the normal read operation is carried out by parallel-comparing the parameter with the plurality of reading reference parameters by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter.

Claim 10

The method of operating the electrically alterable non-volatile multi-level memory according to claim 7, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 11

The method of operating the electrically alterable non-volatile multi-level memory according to claim 8, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 12

The method of operating the electrically alterable non-volatile multi-level memory according to claim 5, wherein, each of the plurality of non-volatile multi-level memory cells has a control gate, and, a control gate of a memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a control gate of non-selected cell.

Claim 13

The method of operating the electrically alterable non-volatile multi-level memory according to claim 6, wherein, each of the plurality of non-volatile multi-level memory cells has a control gate, and, a control gate of a memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a control gate of non-selected cell.

Claim 14

The method of operating the electrically alterable non-volatile multi-level memory according to claim 9, wherein, each of the plurality of non-volatile multi-level memory cells has a control gate, and, a control gate of a memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a control gate of non-selected cell.

Claim 15

The method of operating the electrically alterable non-volatile multi-level memory according to claim 10, wherein, each of the plurality of non-volatile multi-level memory cells has a control gate, and, a control gate of a memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a control gate of non-selected cell.

Claim 16

For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, and reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell, wherein the operation for controlling the electrical value includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programming pulse supplied to the bit line, and wherein the program operation is carried out by variable length programming pulses, the variable length programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first programming pulse has a first programming term and the second programming pulse has a second programming term being shorter than the first programming term.

Claim 17

For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, and reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell, wherein the operation for controlling the electrical value includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programming pulse supplied to the bit line, and wherein the program operation is carried out by variable length programming pulses, the variable length programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first programming pulse has a first programming term and the second programming pulse has a second programming term being shorter than the first programming term.

Claim 18

The method of operating the electrically alterable non-volatile multi-level memory according to claim 15, wherein the variable length programming pulses grow progressively shorter as the one non-volatile multi-level memory cell approaches an appropriate voltage threshold.

Claim 19

The method of operating the electrically alterable non-volatile multi-level memory according to claim 15, further comprising, verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the operation for reading the status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, and wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.

Claim 20

The method of operating the electrically alterable non-volatile multi-level memory according to claim 17, wherein the normal read operation is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value.

Claim 21

The method of operating the electrically alterable non-volatile multi-level memory according to claim 17, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 22

The method of operating the electrically alterable non-volatile multi-level memory according to claim 18, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 23

The method of operating the electrically alterable non-volatile multi-level memory according to claim 16, further comprising, verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the operation for reading the status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, and wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.

Claim 24

The method of operating the electrically alterable non-volatile multi-level memory according to claim 21, wherein the normal read operation is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value.

Claim 25

The method of operating the electrically alterable non-volatile multi-level memory according to claim 21, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 26

The method of operating the electrically alterable non-volatile multi-level memory according to claim 22, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 27

The method of operating the electrically alterable non-volatile multi-level memory according to claim 19, wherein, each of the plurality of non-volatile multi-level memory cells has a control gate, and, a control gate of a memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a control gate of non-selected cell.

Claim 28

The method of operating the electrically alterable non-volatile multi-level memory according to claim 20, wherein, each of the plurality of non-volatile multi-level memory cells has a control gate, and, a control gate of a memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a control gate of non-selected cell.

Claim 29

The method of operating the electrically alterable non-volatile multi-level memory according to claim 23, wherein, each of the plurality of non-volatile multi-level memory cells has a control gate, and, a control gate of a memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a control gate of non-selected cell.

Claim 30

The method of operating the electrically alterable non-volatile multi-level memory according to claim 24, wherein, each of the plurality of non-volatile multi-level memory cells has a control gate, and, a control gate of a memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a control gate of non-selected cell.

Claim 31

For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a control gate, a floating gate and a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, and reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell, wherein the operation for settling the parameter includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programming pulse to a control gate of a memory cell to be programmed, and wherein the program operation is carried out by variable length programming pulses, the variable length programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first programming pulse has a first programming term and the second programming pulse has a second programming term being shorter than the first programming term.

Claim 32

For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a control gate, a floating gate and a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, and reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell, wherein the operation for settling the parameter includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programming pulse to a control gate of a memory cell to be programmed, and wherein the program operation is carried out by variable length programming pulses, the variable length programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first programming pulse has a first programming term and the second programming pulse has a second programming term being shorter than the first programming term.

Claim 33

The method of operating the electrically alterable non-volatile multi-level memory according to claim 29, wherein the variable length programming pulses grow progressively shorter as the one non-volatile multi-level memory cell approaches an appropriate voltage threshold.

Claim 34

The method of operating the electrically alterable non-volatile multi-level memory according to claim 30, further comprising, verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the operation for reading the status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, and wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.

Claim 35

The method of operating the electrically alterable non-volatile multi-level memory according to claim 31, wherein the normal read operation is carried out by parallel-comparing the parameter with the plurality of reading reference parameters by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter.

Claim 36

The method of operating the electrically alterable non-volatile multi-level memory according to claim 31, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 37

The method of operating the electrically alterable non-volatile multi-level memory according to claim 32, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 38

The method of operating the electrically alterable non-volatile multi-level memory according to claim 30, further comprising, verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the operation for reading the status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, and wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.

Claim 39

The method of operating the electrically alterable non-volatile multi-level memory according to claim 35, wherein the normal read operation is carried out by parallel-comparing the parameter with the plurality of reading reference parameters by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter.

Claim 40

The method of operating the electrically alterable non-volatile multi-level memory according to claim 35, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 41

The method of operating the electrically alterable non-volatile multi-level memory according to claim 36, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 42

The method of operating the electrically alterable non-volatile multi-level memory according to claim 33, wherein a bit line coupled with said memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a bit line coupled with non-selected cell.

Claim 43

The method of operating the electrically alterable non-volatile multi-level memory according to claim 34, wherein a bit line coupled with said memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a bit line coupled with non-selected cell.

Claim 44

The method of operating the electrically alterable non-volatile multi-level memory according to claim 37, wherein a bit line coupled with said memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a bit line coupled with non-selected cell.

Claim 45

The method of operating the electrically alterable non-volatile multi-level memory according to claim 38, wherein a bit line coupled with said memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a bit line coupled with non-selected cell.

Claim 46

For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, and reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell, wherein the operation for controlling the electrical value includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programming pulse to a control gate of a memory cell to be programmed, and wherein the program operation is carried out by variable length programming pulses, the variable length programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first programming pulse has a first programming term and the second programming pulse has a second programming term being shorter than the first programming term.

Claim 47

For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, and reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell, wherein the operation for controlling the electrical value includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programming pulse to a control gate of a memory cell to be programmed, and wherein the program operation is carried out by variable length programming pulses, the variable length programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first programming pulse has a first programming term and the second programming pulse has a second programming term being shorter than the first programming term.

Claim 48

The method of operating the electrically alterable non-volatile multi-level memory according to claim 43, wherein the variable length programming pulses grow progressively shorter as the one non-volatile multi-level memory cell approaches an appropriate voltage threshold.

Claim 49

The method of operating the electrically alterable non-volatile multi-level memory according to claim 43, further comprising, verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the operation for reading the status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, and wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.

Claim 50

The method of operating the electrically alterable non-volatile multi-level memory according to claim 45, wherein the normal read operation is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value.

Claim 51

The method of operating the electrically alterable non-volatile multi-level memory according to claim 45, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 52

The method of operating the electrically alterable non-volatile multi-level memory according to claim 46, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 53

The method of operating the electrically alterable non-volatile multi-level memory according to claim 44, further comprising, verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the operation for reading the status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, and wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.

Claim 54

The method of operating the electrically alterable non-volatile multi-level memory according to claim 49, wherein the normal read operation is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value.

Claim 55

The method of operating the electrically alterable non-volatile multi-level memory according to claim 49, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 56

The method of operating the electrically alterable non-volatile multi-level memory according to claim 50, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 57

The method of operating the electrically alterable non-volatile multi-level memory according to claim 47, wherein a bit line coupled with said memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a bit line coupled with non-selected cell.

Claim 58

The method of operating the electrically alterable non-volatile multi-level memory according to claim 48, wherein a bit line coupled with said memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a bit line coupled with non-selected cell.

Claim 59

The method of operating the electrically alterable non-volatile multi-level memory according to claim 51, wherein a bit line coupled with said memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a bit line coupled with non-selected cell.

Claim 60

The method of operating the electrically alterable non-volatile multi-level memory according to claim 52, wherein a bit line coupled with said memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a bit line coupled with non-selected cell.

Claim 61

An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate: wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein an operation for reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell is carried out, wherein the operation for settling the parameter includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programming pulse supplied to the bit line, and wherein the program operation is carried out by variable length programming pulses, the variable length programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first programming pulse has a first programming term and the second programming pulse has a second programming term being shorter than the first programming term.

Claim 62

An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate: wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein an operation for reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell is carried out, wherein the operation for settling the parameter includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programming pulse supplied to the bit line, and wherein the program operation is carried out by variable length programming pulses, the variable length programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first programming pulse has a first programming term and the second programming pulse has a second programming term being shorter than the first programming term.

Claim 63

The electrically alterable non-volatile multi-level memory according to claim 57, wherein the variable length programming pulses grow progressively shorter as the one non-volatile multi-level memory cell approaches an appropriate voltage threshold.

Claim 64

The electrically alterable non-volatile multi-level memory according to claim 57, further comprising, verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the operation for reading the status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, and wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.

Claim 65

The electrically alterable non-volatile multi-level memory according to claim 59, wherein the normal read operation is carried out by parallel-comparing the parameter with the plurality of reading reference parameters by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter.

Claim 66

The electrically alterable non-volatile multi-level memory according to claim 59, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 67

The electrically alterable non-volatile multi-level memory according to claim 60, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 68

The electrically alterable non-volatile multi-level memory according to claim 58, further comprising, an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the operation for reading the status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, and wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.

Claim 69

The electrically alterable non-volatile multi-level memory according to claim 63, wherein the normal read operation is carried out by parallel-comparing the parameter with the plurality of reading reference parameters by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter.

Claim 70

The electrically alterable non-volatile multi-level memory according to claim 63, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 71

The electrically alterable non-volatile multi-level memory according to claim 64, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 72

The electrically alterable non-volatile multi-level memory according to claim 61, wherein, each of the plurality of non-volatile multi-level memory cells has a control gate, and, a control gate of a memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a control gate of non-selected cell.

Claim 73

The electrically alterable non-volatile multi-level memory according to claim 62, wherein, each of the plurality of non-volatile multi-level memory cells has a control gate, and, a control gate of a memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a control gate of non-selected cell.

Claim 74

The electrically alterable non-volatile multi-level memory according to claim 65, wherein, each of the plurality of non-volatile multi-level memory cells has a control gate, and, a control gate of a memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a control gate of non-selected cell.

Claim 75

The electrically alterable non-volatile multi-level memory according to claim 66, wherein, each of the plurality of non-volatile multi-level memory cells has a control gate, and, a control gate of a memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a control gate of non-selected cell.

Claim 76

An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate: wherein an operation for controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein an operation for reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell is carried out, wherein the operation for controlling the electrical value includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programming pulse supplied to the bit line, and wherein the program operation is carried out by variable length programming pulses, the variable length programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first programming pulse has a first programming term and the second programming pulse has a second programming term being shorter than the first programming term.

Claim 77

An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate: wherein an operation for controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein an operation for reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell is carried out, wherein the operation for controlling the electrical value includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programming pulse supplied to the bit line, and wherein the program operation is carried out by variable length programming pulses, the variable length programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first programming pulse has a first programming term and the second programming pulse has a second programming term being shorter than the first programming term.

Claim 78

The electrically alterable non-volatile multi-level memory according to claim 71, wherein the variable length programming pulses grow progressively shorter as the one non-volatile multi-level memory cell approaches an appropriate voltage threshold.

Claim 79

The electrically alterable non-volatile multi-level memory according to claim 71, further comprising, an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the operation for reading the status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, and wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.

Claim 80

The electrically alterable non-volatile multi-level memory according to claim 73, wherein the normal read operation is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value.

Claim 81

The electrically alterable non-volatile multi-level memory according to claim 73, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 82

The method of operating the electrically alterable non-volatile multi-level memory according to claim 74, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 83

The electrically alterable non-volatile multi-level memory according to claim 72, further comprising an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the operation for reading the status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, and wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.

Claim 84

The electrically alterable non-volatile multi-level memory according to claim 77, wherein the normal read operation is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value.

Claim 85

The electrically alterable non-volatile multi-level memory according to claim 77, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 86

The electrically alterable non-volatile multi-level memory according to claim 78, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 87

The electrically alterable non-volatile multi-level memory according to claim 75, wherein each of the plurality of non-volatile multi-level memory cells has a control gate, and, a control gate of a memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a control gate of non-selected cell.

Claim 88

The electrically alterable non-volatile multi-level memory according to claim 76, wherein, each of the plurality of non-volatile multi-level memory cells has a control gate, and, a control gate of a memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a control gate of non-selected cell.

Claim 89

The electrically alterable non-volatile multi-level memory according to claim 79, wherein, each of the plurality of non-volatile multi-level memory cells has a control gate, and, a control gate of a memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a control gate of non-selected cell.

Claim 90

The electrically alterable non-volatile multi-level memory according to claim 80, wherein, each of the plurality of non-volatile multi-level memory cells has a control gate, and, a control gate of a memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a control gate of non-selected cell.

Claim 91

An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a control gate, a floating gate and a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein an operation for reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell is carried out, wherein the operation for settling the parameter includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programming pulse to a control gate of a memory cell to be programmed, and wherein the program operation is carried out by variable length programming pulses, the variable length programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first programming pulse has a first programming term and the second programming pulse has a second programming term being shorter than the first programming term.

Claim 92

An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a control gate, a floating gate and a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: wherein an operation for settling a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein an operation for reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell is carried out, wherein the operation for settling the parameter includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programming pulse to a control gate of a memory cell to be programmed, and wherein the program operation is carried out by variable length programming pulses, the variable length programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first programming pulse has a first programming term and the second programming pulse has a second programming term being shorter than the first programming term.

Claim 93

The electrically alterable non-volatile multi-level memory according to claim 85, wherein the variable length programming pulses grow progressively shorter as the one non-volatile multi-level memory cell approaches an appropriate voltage threshold.

Claim 94

The electrically alterable non-volatile multi-level memory according to claim 85, further comprising, an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the operation for reading the status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, and wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.

Claim 95

The electrically alterable non-volatile multi-level memory according to claim 87, wherein the normal read operation is carried out by parallel-comparing the parameter with the plurality of reading reference parameters by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter.

Claim 96

The electrically alterable non-volatile multi-level memory according to claim 87, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 97

The electrically alterable non-volatile multi-level memory according to claim 88, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 98

The electrically alterable non-volatile multi-level memory according to claim 86, further comprising, an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the operation for reading the status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, and wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.

Claim 99

The electrically alterable non-volatile multi-level memory according to claim 91, wherein the normal read operation is carried out by parallel-comparing the parameter with the plurality of reading reference parameters by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter.

Claim 100

The electrically alterable non-volatile multi-level memory according to claim 91, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 101

The electrically alterable non-volatile multi-level memory according to claim 92, wherein the operation for settling the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 102

The electrically alterable non-volatile multi-level memory according to claim 89, wherein a bit line coupled with said memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a bit line coupled with non-selected cell.

Claim 103

The electrically alterable non-volatile multi-level memory according to claim 90, wherein a bit line coupled with said memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a bit line coupled with non-selected cell.

Claim 104

The electrically alterable non-volatile multi-level memory according to claim 93, wherein a bit line coupled with said memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a bit line coupled with non-selected cell.

Claim 105

The electrically alterable non-volatile multi-level memory according to claim 94, wherein a bit line coupled with said memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a bit line coupled with non-selected cell.

Claim 106

An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: wherein an operation for controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein an operation for reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell is carried out, wherein the operation for controlling the electrical value includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programming pulse to a control gate of a memory cell to be programmed, and wherein the program operation is carried out by variable length programming pulses, the variable length programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first programming pulse has a first programming term and the second programming pulse has a second programming term being shorter than the first programming term.

Claim 107

An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: wherein an operation for controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, and wherein an operation for reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell is carried out, wherein the operation for controlling the electrical value includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell by applying at least one programming pulse to a control gate of a memory cell to be programmed, and wherein the program operation is carried out by variable length programming pulses, the variable length programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, the first programming pulse has a first programming term and the second programming pulse has a second programming term being shorter than the first programming term.

Claim 108

The electrically alterable non-volatile multi-level memory according to claim 99, wherein the variable length programming pulses grow progressively shorter as the one non-volatile multi-level memory cell approaches an appropriate voltage threshold.

Claim 109

The electrically alterable non-volatile multi-level memory according to claim 99, further comprising, an operation for verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the operation for reading the status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, and wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.

Claim 110

The electrically alterable non-volatile multi-level memory according to claim 101, wherein the normal read operation is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value.

Claim 111

The electrically alterable non-volatile multi-level memory according to claim 101, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 112

The electrically alterable non-volatile multi-level memory according to claim 102, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 113

The electrically alterable non-volatile multi-level memory according to claim 100, further comprising, wherein an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has being settled to the one state selected from the plurality of states by comparing the parameter of the one non-volatile multi-level memory cell with a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter, a third verifying reference parameter and a fourth verifying reference parameter, and of repeating the operation for settling the parameter and the operation for verifying until it is verified by the operation for verifying that the parameter of the one non-volatile multi-level memory cell has being settled to the one state, wherein the operation for reading the status of the one non-volatile multi-level memory cell is carried out by comparing the parameter with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is decreased in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, and wherein the first verifying reference parameter is allocated below the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter, the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter and the fourth verifying reference parameter is allocated above the third reading reference parameter.

Claim 114

The electrically alterable non-volatile multi-level memory according to claim 105, wherein the normal read operation is carried out by parallel-comparing the electrical value with the plurality of reading reference electrical values by using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value.

Claim 115

The electrically alterable non-volatile multi-level memory according to claim 105, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 116

The electrically alterable non-volatile multi-level memory according to claim 106, wherein the operation for controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 117

The electrically alterable non-volatile multi-level memory according to claim 103, wherein a bit line coupled with said memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a bit line coupled with non-selected cell.

Claim 118

The electrically alterable non-volatile multi-level memory according to claim 104, wherein a bit line coupled with said memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a bit line coupled with non-selected cell.

Claim 119

The electrically alterable non-volatile multi-level memory according to claim 107, wherein a bit line coupled with said memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a bit line coupled with non-selected cell.

Claim 120

The electrically alterable non-volatile multi-level memory according to claim 108, wherein a bit line coupled with said memory cell to be programmed is supplied with a predetermined potential which is different from a potential being supplied to a bit line coupled with non-selected cell.