Patent US6351406B1 successfully refreshed from Google Patents.
US6351406B1
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Vertically stacked field programmable nonvolatile memory and method of fabrication
Assignee: SanDisk Technologies LLC
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Filing: 2000-11-15
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Granted: 2002-02-26
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Expires: 2020-11-15
Abstract
Abstract A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
Inventors
- 👤 Mark G. Johnson
- 👤 Thomas H. Lee
- 👤 Vivek Subramanian
- 👤 P. Michael Farmwald
- 👤 James M. Cleeves
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 16:07
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C11/00; G11C11/56; G11C11/5692; G11C13/00; G11C13/0002; G11C13/0021; G11C13/003; G11C2213/00; G11C2213/70; G11C2213/71; G11C2213/76
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
110 words
A memory comprising: a semiconductor substrate having peripheral circuits for the memory; a memory array having a plurality of levels where each level includes a plurality of memory cells formed above the substrate, the memory cells at each level being coupled to a plurality of first and second lines; and a plurality of vias for providing electrical connections between at least the first lines in more than one of the levels and the peripheral circuits of the substrate, each of the vias extending through more than one of the levels and contacting first lines in more than one level such that fewer than one via mask is needed per level.
Claim 2
Dependent Claim
110 words
A memory comprising: a semiconductor substrate having peripheral circuits for the memory; a memory array having a plurality of levels where each level includes a plurality of memory cells formed above the substrate, the memory cells at each level being coupled to a plurality of first and second lines; and a plurality of vias for providing electrical connections between at least the first lines in more than one of the levels and the peripheral circuits of the substrate, each of the vias extending through more than one of the levels and contacting first lines in more than one level such that fewer than one via mask is needed per level.
Claim 3
Dependent Claim
17 words
The memory defined by claim 1 wherein the first and second lines are perpendicular to one another.
Claim 4
Dependent Claim
11 words
The memory defined by claim 2 wherein the substrate is silicon.
Claim 5
Dependent Claim
15 words
The memory defined by claim 2 or 3 wherein the vias are rectangular in shape.
Claim 6
Dependent Claim
11 words
The memory defined by claims 4 wherein the vias contain polysilicon.
Claim 7
Dependent Claim
23 words
The memory defined by claim 5 wherein the vias provide connections between the second lines more than one level and the peripheral circuits.
Claim 8
Dependent Claim
16 words
The memory defined by claim 1 wherein each memory cell comprising a diode and an antifuse.
Claim 9
Dependent Claim
44 words
The memory defined by claim 7 wherein one of the first and second lines in one of the plurality of layers makes electrical contact with a region of the same conductivity type of the diode in two of the levels of the memory array.
Claim 10
Dependent Claim
14 words
The memory defined by claim 8 wherein the vias have a rectangular cross section.
Claim 11
Dependent Claim
49 words
A memory comprising: a semiconductor substrate; and a plurality of separate three dimensional arrays of memory cells nestled with respect to one another on the substrate, each array comprising a plurality of levels of memory cells, the cells in each array communicating with peripheral circuits disposed in the substrate.
Claim 12
Dependent Claim
49 words
A memory comprising: a semiconductor substrate; and a plurality of separate three dimensional arrays of memory cells nestled with respect to one another on the substrate, each array comprising a plurality of levels of memory cells, the cells in each array communicating with peripheral circuits disposed in the substrate.
Claim 13
Dependent Claim
26 words
The memory defined by claim 10 wherein the peripheral circuits associated with each of the arrays has a layout having tabs at corners of the arrays.
Claim 14
Dependent Claim
11 words
The memory defined by claim 11 wherein the tabs are interdigitated.
Claim 15
Dependent Claim
36 words
The memory defined by claim 10 wherein each level has a plurality of first line and plurality of second lines generally perpendicular to the first lines, the first and second lines being connected to the cells.
Claim 16
Dependent Claim
65 words
The memory defined by claim 13 includes a plurality of vias for providing electrical connections between at least the first lines in the plurality of levels and the peripheral circuits of the substrate, each of the vias extending through more than one of the levels and contacting first lines in more than one level such that fewer than one via mask is needed per level.
Claim 17
Dependent Claim
11 words
The memory defined by claim 14 wherein the substrate is silicon.
Claim 18
Dependent Claim
48 words
A memory comprising: a substrate; a three dimensional memory array disposed on the substrate having a plurality of cells disposed in a plurality of levels; the substrate including a plurality of decoders for accessing the cells with at least some of the decoders being folded under the array.
Claim 19
Dependent Claim
48 words
A memory comprising: a substrate; a three dimensional memory array disposed on the substrate having a plurality of cells disposed in a plurality of levels; the substrate including a plurality of decoders for accessing the cells with at least some of the decoders being folded under the array.
Claim 20
Dependent Claim
32 words
The memory defined by claim 16 wherein the decoders include both column decoders and row decoders with one of the column and row decoders being folded under the array in the substrate.
Claim 21
Dependent Claim
25 words
The memory defined by claim 17 wherein the plurality of cells disposed in a plurality of levels include a plurality of first and second lines.
Claim 22
Dependent Claim
64 words
The memory defined by claim 18 including a plurality of vias for providing electrical connections between at least the first lines in the plurality of levels and the decoders of the substrate, each of the vias extending through more than one of the levels and contacting first lines in more than one level such that fewer than one via mask is needed per level.
Claim 23
Dependent Claim
21 words
The memory defined by claim 18 or 19 wherein each cell of the memory array includes a diode and an antifuse.
Claim 24
Dependent Claim
11 words
The memory defined by claim 20 wherein the substrate is silicon.
Claim 25
Dependent Claim
99 words
A memory comprising: a semiconductor substrate; a memory array comprising a plurality of levels, each level having a plurality of column lines, a plurality of row lines and a plurality of memory cells, with a column line in a level n also being a column line in a level n+1 and a row line in level n also being a row line in level n−1; the substrate containing column decoders and row decoders coupled to the column and row lines, respectively, with at least a part of one of the row and column decoders being disposed under the array.
Claim 26
Dependent Claim
99 words
A memory comprising: a semiconductor substrate; a memory array comprising a plurality of levels, each level having a plurality of column lines, a plurality of row lines and a plurality of memory cells, with a column line in a level n also being a column line in a level n+1 and a row line in level n also being a row line in level n−1; the substrate containing column decoders and row decoders coupled to the column and row lines, respectively, with at least a part of one of the row and column decoders being disposed under the array.
Claim 27
Dependent Claim
22 words
The memory defined by claim 22 wherein the substrate includes circuits for sensing the state of the cells in a current mode.
Claim 28
Dependent Claim
64 words
The memory defined by claim 22 including a plurality of vias for providing electrical connections between at least the column lines in the plurality of levels and the decoders of the substrate, each of the vias extending through more than one of the levels and contacting column lines in more than one level such that fewer than one via mask is needed per level.
Claim 29
Dependent Claim
11 words
The memory defined by claim 24 wherein the substrate is silicon.
Claim 30
Dependent Claim
16 words
The memory defined by claim 25 wherein each memory cell comprises a diode and an antifuse.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-02-25 | 2005-08-27 | 2006-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-02-25 | 2009-08-27 | 2010-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-02-25 | 2013-08-27 | 2014-02-26 | $7700.00 | Window Closed / Lapsed |