US5942913A
Expired / Lapsed
US
⏱️ 0.0 years remaining
FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines
Assignee: Xilinx Inc
•
Filing: 1997-03-20
•
Granted: 1999-08-24
•
Expires: 2017-03-20
Abstract
Abstract The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. The interconnect structure includes both buffered and unbuffered interconnect lines. Some buffered interconnect lines are bidirectional, and others are unidirectional. A carefully selected mixture of unidirectional and bidirectional lines provides a balance of flexibility, silicon area, and performance.
Inventors
- 👤 Steven P. Young
- 👤 Trevor J. Bauer
- 👤 Kamal Chaudhary
- 👤 Sridhar Krishnamurthy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:27
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/1778
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
73 words
An FPGA comprising: a plurality of logic blocks; and a plurality of interconnect lines each separately interconnecting first and second such logic blocks, some of said interconnect lines being buffered and some others of said interconnect lines being unbuffered, wherein: some of said buffered interconnect lines connecting said first and second such logic blocks are bidirectional and some others of said buffered interconnect lines connecting said first and second logic blocks are unidirectional.
Claim 2
Dependent Claim
73 words
An FPGA comprising: a plurality of logic blocks; and a plurality of interconnect lines each separately interconnecting first and second such logic blocks, some of said interconnect lines being buffered and some others of said interconnect lines being unbuffered, wherein: some of said buffered interconnect lines connecting said first and second such logic blocks are bidirectional and some others of said buffered interconnect lines connecting said first and second logic blocks are unidirectional.
Claim 3
Dependent Claim
24 words
The FPGA of claim 1, wherein the ratio of unidirectional buffered interconnect lines to bidirectional buffered interconnect lines is at least two to one.
Claim 4
Dependent Claim
24 words
The FPGA of claim 1, wherein the ratio of unidirectional buffered interconnect lines to bidirectional buffered interconnect lines is at least four to one.
Claim 5
Dependent Claim
93 words
An FPGA comprising: an array of tiles, each tile comprising: a logic block; a plurality of PIPs; and a plurality of line segments, each such line segment abutting another such line segment in an adjacent such tile to form a plurality of interconnect lines each separately interconnecting first and second such logic blocks in such tiles through said PIPs, wherein: some of said interconnect lines programmably connecting two non-adjacent such logic blocks are buffered; and some of said buffered interconnect lines are bidirectional and some others of said buffered interconnect lines are unidirectional.
Claim 6
Dependent Claim
93 words
An FPGA comprising: an array of tiles, each tile comprising: a logic block; a plurality of PIPs; and a plurality of line segments, each such line segment abutting another such line segment in an adjacent such tile to form a plurality of interconnect lines each separately interconnecting first and second such logic blocks in such tiles through said PIPs, wherein: some of said interconnect lines programmably connecting two non-adjacent such logic blocks are buffered; and some of said buffered interconnect lines are bidirectional and some others of said buffered interconnect lines are unidirectional.
Claim 7
Dependent Claim
28 words
The FPGA of claim 4, wherein: some of said bidirectional buffered interconnect lines traverse the same number of such tiles as some of said unidirectional buffered interconnect lines.
Claim 8
Dependent Claim
24 words
The FPGA of claim 5 wherein the ratio of unidirectional buffered interconnect lines to bidirectional buffered interconnect lines is at least four to one.
Claim 9
Dependent Claim
25 words
The FPGA of claim 5, wherein: some of said bidirectional buffered interconnect lines traverse the same tiles as some of said unidirectional buffered interconnect lines.
Claim 10
Dependent Claim
24 words
The FPGA of claim 5, wherein the ratio of unidirectional buffered interconnect lines to bidirectional buffered interconnect lines is at least two to one.
Claim 11
Dependent Claim
98 words
An FPGA comprising: an array of tiles, each tile comprising: a logic block; a plurality of PIPs; and a plurality of line segments, each such line segment abutting another such line segment in an adjacent such tile to form a plurality of interconnect lines each separately interconnecting first and second such logic blocks in such tiles through said PIPs, wherein: some of said interconnect lines connecting two such logic blocks are buffered; and some of said buffered interconnect lines connecting the same two such logic blocks are bidirectional and some others of said buffered interconnect lines are unidirectional.
Claim 12
Dependent Claim
98 words
An FPGA comprising: an array of tiles, each tile comprising: a logic block; a plurality of PIPs; and a plurality of line segments, each such line segment abutting another such line segment in an adjacent such tile to form a plurality of interconnect lines each separately interconnecting first and second such logic blocks in such tiles through said PIPs, wherein: some of said interconnect lines connecting two such logic blocks are buffered; and some of said buffered interconnect lines connecting the same two such logic blocks are bidirectional and some others of said buffered interconnect lines are unidirectional.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-23 | 2003-02-22 | 2003-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-23 | 2007-02-22 | 2007-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-23 | 2011-02-22 | 2011-08-24 | $7700.00 | Window Closed / Lapsed |