Abstract The present invention provides power up detect circuit for generating a reset signal for a logic circuit that includes N-channel transistors having a threshold value Vnth and P-channel transistors having a threshold value Vpth. The power-up detect circuit includes comparison means having first and second inputs; clamping means for clamping the first comparison means input at X*Vnth above ground potential; and monitoring means connected to the second comparison means input and responsive to ramp up of a power supply voltage for holding the second comparison means input at X*Vpth less than the power supply voltage whereby the comparison means output switches from an inactive state to an active state when the power supply to ground potential reaches (X*Vnth)+(X*Vpth). The power up detect circuit further includes hysteresis means connected between the comparison means output and the second comparison means input and responsive to the power supply for preventing the comparison means output from switching from the active state to the machine state if the power supply voltage remains above (X*Vnth+Y*Vpth)-(WVnth+ZVpth), where 0<W<X, 0<Z<Y).
A power up detect circuit for generating a reset signal for a logic circuit that includes N-channel transistors having a threshold value Vnth and P-channel transistors having a threshold value Vpth, the power-up detect circuit comprising: comparison means having first and second inputs; clamping means for clamping the first comparison means input at X*Vnth above ground potential; monitoring means connected to the second comparison means input and responsive to ramp up of a power supply voltage for holding the second comparison means input at Y*Vpth less than the power supply voltage whereby the comparison means output switches from an inactive state to an active state when the power supply to ground potential reaches (X*Vnth)+(Y*Vpth); and hysteresis means connected between the comparison means output and the second comparison means input and responsive to the power supply for preventing the comparison means output from switching from the active state to the inactive state if the power supply voltage remains above (V*Vnth+Y*Vpth)-(WVnth+ZVpth), where O<W<X, O<Z<Y).
Claim 2
Dependent Claim
162 words
A power up detect circuit for generating a reset signal for a logic circuit that includes N-channel transistors having a threshold value Vnth and P-channel transistors having a threshold value Vpth, the power-up detect circuit comprising: comparison means having first and second inputs; clamping means for clamping the first comparison means input at X*Vnth above ground potential; monitoring means connected to the second comparison means input and responsive to ramp up of a power supply voltage for holding the second comparison means input at Y*Vpth less than the power supply voltage whereby the comparison means output switches from an inactive state to an active state when the power supply to ground potential reaches (X*Vnth)+(Y*Vpth); and hysteresis means connected between the comparison means output and the second comparison means input and responsive to the power supply for preventing the comparison means output from switching from the active state to the inactive state if the power supply voltage remains above (V*Vnth+Y*Vpth)-(WVnth+ZVpth), where O<W<X, O<Z<Y).