Signal generator circuit

Claim 2

A signal generator circuit characterized by comprising at least first and second flip-flops which are first stabilized to one value when a power supply is energized, memory means, a logical product circuit, and first and second pulse signals which arrive periodically and which differ in phase, said first pulse signal being applied to an inversion input terminal of said first flip-flop, an inversion output signal of this flip-flop being stored in synchronism with said second pulse signal by said memory means provided at one input of said logical product circuit, said first pulse signal being applied to the other input of said logical product circuit, an output thereof being applied to an inversion input terminal of said second flip-flop, an inversion output signal of said second flip-flop being made an output signal.

Claim 3

A signal generator comprising: a power supply; first and second periodic pulse signal sources being of different phases; a first flip-flop, and at least one additional flip-flop, wherein a predetermined stable state occurs upon the energization of said power supply; a plurality of logical product circuits each having one input connected to said first pulse source and each having its output connected to the input of its respective additional flip-flop; a plurality of memory means, each having its write input connected to said second pulse source, its data input being connected to the output of its respective flip-flop, and its output connected to the second input of said respective logical product circuit; said first pulse source being connected to the input of said first flip-flop; wherein the output signal is obtained from the output terminal of the last additional flip-flop.

Claim 4

A signal generator comprising: a power supply; first and second periodic pulse signal sources being of different phases; a first flip-flop, and at least one additional flip-flop, wherein a predetermined stable state occurs upon the energization of said power supply; a plurality of logical product circuits each having one input connected to said first pulse source and each having its output connected to the input of its respective additional flip-flop; a plurality of memory means, each having its write input connected to said second pulse source, its data input being connected to the output of its respective flip-flop, and its output connected to the second input of said respective logical product circuit; said first pulse source being connected to the input of said first flip-flop; wherein the output signal is obtained from the output terminal of the last additional flip-flop.

Claim 5

A signal generator as in claim 2, wherein said flip-flops are formed from cross-connected insulated gate field effect transistors, and the transistor loads are constructed from an additional pair of insulated gate field effect transistors, one of which being of the enhancement type and the other of the depletion type.

Claim 6

A signal generator as in claim 2, wherein said logical product circuit is formed from a pair of series connected insulated gate field effect transistors.

Claim 7

A signal generator as in claim 2, wherein the memory means comprises an insulated gate field effect transistor having an additional insulated gate field effect transistor as its load element.

Claim 8

A signal generator as in claim 3, wherein an additional depletion type insulated gate field effect transistor is connected from said flip-flop output terminal to said power supply return terminal.

Claim 9

A signal generator comprising: a power supply; first and second periodic pulse signal sources being of different phases; a first and a second flip-flop, each composed of cross-connected insulated gate field effect transistors with the transistor loads being composed of an additional pair of insulated gate field effect transistors, one of which being of the enhancement type and the other of the depletion type; a logical product circuit, composed of two series connected insulated gate field effect transistors, with the gate of one transistor connected to said first pulse source and the gate of the second transistor connected through a memory circuit means to the output terminal of the first flip-flop, and the output of the logical product circuit connected to the input terminal of the second flip-flop; said memory circuit means being composed of an insulated gate field effect transistor having its gate connected to said second pulse signal source and using an additional insulated gate field effect transistor as its load element; an additional two depletion type insulated gate type field effect transistors each of which is connected between the output terminals of one of said flip-flops to said power supply return terminal; wherein said first pulse source being connected to the input of the first flip-flop and the output signal is obtained from the output terminal of the second flip-flop.

Claim 10

A signal generator comprising: a power supply; first and second periodic pulse signal sources being of different phases; a first and a second flip-flop, each composed of cross-connected insulated gate field effect transistors with the transistor loads being composed of an additional pair of insulated gate field effect transistors, one of which being of the enhancement type and the other of the depletion type; a logical product circuit, composed of two series connected insulated gate field effect transistors, with the gate of one transistor connected to said first pulse source and the gate of the second transistor connected through a memory circuit means to the output terminal of the first flip-flop, and the output of the logical product circuit connected to the input terminal of the second flip-flop; said memory circuit means being composed of an insulated gate field effect transistor having its gate connected to said second pulse signal source and using an additional insulated gate field effect transistor as its load element; an additional two depletion type insulated gate type field effect transistors each of which is connected between the output terminals of one of said flip-flops to said power supply return terminal; wherein said first pulse source being connected to the input of the first flip-flop and the output signal is obtained from the output terminal of the second flip-flop.