US3858061A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple size gates on fet chips
Assignee: International Business Machines Corp
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Filing: 1972-12-27
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Granted: 1974-12-31
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Expires: 1992-12-27
Abstract
Abstract Variation of the gate size of an FET gate may be used to vary the interelectrode capacitance of the FET, thus varying the turn on time of the FET. By varying the gate size of individual FETs on a single chip, the turn on times of the FETs within a particular logic circuit will be different, and these time differences can be used to eliminate races or to equalize the delays along signal paths within the logic circuit. Because the interelectrode capacitance is used to effect the delays, additional delay circuits are not required. Furthermore, by proper arrangement of the FETs the turn on sequence of FETs within a logic circuit can be predicted and thus the response of a logic circuit to a test pattern can be predicted.
Inventors
- 👤 R Carpenter
- 👤 M Mcmahon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:37
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/01; H03K3/013; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/173; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
174 words
In an integrated circuit including a plurality of FETs connected to form at least one circuit having more than one signal path, each signal path having different signal delays, the improvement providing equalization of the delays in the signal paths through said integrated circuit comprising: a. at least one first FET in a first of said signal paths having a first gate electrode, said first gate electrode having a first predetermined size determining the inter-electrode capacitance of said first FET which, in turn, defines a first turn-on time for said first FET; and b. at least one second FET in a second signal path having a second gate electrode, said second gate electrode having a second predetermined size different from said first predetermined size and determining the inter-electrode capacitance of said second FET which, in turn, defines a Second turn-on time different from said first turn-on time for said second FET, said first and second turn-on times being chosen to equalize the delays in said first and second signal paths through said integrated circuit.
Claim 2
Dependent Claim
174 words
In an integrated circuit including a plurality of FETs connected to form at least one circuit having more than one signal path, each signal path having different signal delays, the improvement providing equalization of the delays in the signal paths through said integrated circuit comprising: a. at least one first FET in a first of said signal paths having a first gate electrode, said first gate electrode having a first predetermined size determining the inter-electrode capacitance of said first FET which, in turn, defines a first turn-on time for said first FET; and b. at least one second FET in a second signal path having a second gate electrode, said second gate electrode having a second predetermined size different from said first predetermined size and determining the inter-electrode capacitance of said second FET which, in turn, defines a Second turn-on time different from said first turn-on time for said second FET, said first and second turn-on times being chosen to equalize the delays in said first and second signal paths through said integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-30 | 1978-07-01 | 1978-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-30 | 1982-07-01 | 1982-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-30 | 1986-07-01 | 1986-12-31 | $7700.00 | Window Closed / Lapsed |