Integrated mos transistor flip-flop circuit

Claim 2

An integrated circuit of enhancement-type MOS transistors comprising two flip-flop stages interconnected to provide J-K capability, wherein: a. each said stage comprises a pair of series circuits for retaining binary logic levels; b. each said series circuit comprises a first enhancement-type MOS transistor to act as an inverter, and a second enhancementtype MOS transistor of the same channel-type as the first transistor to act as a load coNnected in series with said inverter transistor, the resistance of said second transistor being higher than that of said first transistor, said integrated circuit further comprising: c. means in each stage directly connecting a first other series circuit of the other of said stages to the gate of the inverter transistor of said first series circuit of said other stage, including means interconnecting said stages, said interconnecting means comprising: f. means including an enhancement-type MOS transistor to act as a third transmission transistor connecting said second common point of said first stage to the gate of the inverter transistor of said first series circuit of said other stage through said third transmission transistor; g. means including an enhancement-type MOS transistor to act as a fourth transmission transistor connecting said first common point of said other stage to the gate of the inverter transistor of said first series circuit of said first stage through said fourth transmission transistor; and h. means for applying clock pulses to the gates of said transmission transistors, comprising means for applying one phase of a two phase clock pulse simultaneously to said first and third transmission transistors and the other phase of said two phase clock pulse simultaneously to said second and fourth transmission transistors.

Claim 3

An integrated circuit according to claim 1 including: j. two further enhancement-type MOS transistors each connected in series with the inverter transistor of a respective one of the series circuits of one of said stages; and k. means connecting the gates of said further transistors to respective terminals for receiving J and K inputs.

Claim 4

An integrated circuit of enhancement-type MOS transistors comprising: a. three flip-flop stages interconnected to provide J-K capability; b. each said stage comprising a pair of series circuits for retaining binary logic levels; c. each said series circuit comprising a first enhancement-type MOS transistor to act as an inverter, and a second enhancement-type MOS transistor to act as a load connected in series with said inverter transistor, the resistance of said second transistor being higher than that of said first transistor; d. means directly connecting the common point between the transistors of a first of said series circuits in each of said stages to the gate of the inverter transistor of the other series circuit of the same stage; e. means including an enhancement-type MOS transistor to act as a feedback transmission transistor connecting the common point between the transistors of said other series circuit in each of said stages to the gate of the inverter transistor of the first series circuit of the same stage through said transmission transistor; f. interstage connecting means including: i. a fourth, enhancement-type MOS transistor to act as a transmission transistor connecting a common point between the transistors of said other series circuit of a first of said stages to the gate of the inverter transistor of the first series circuit of a second of said stages through said fourth transistor, ii. a fifth, enhancement-type MOS transistor to act as a transmission transistor connecting a common point between the transistors of said other series circuit of the second stage to the gate of the inverter transistor of the first series circuit of the third stage through said fifth transistor, iii. a sixth, enhancement-type MOS transistor to act as a transmission transistor connecting a common point between the transistors of the first series circuit of the second stage to the gate of the inverter transistor of said first series circuit of the first stage; and g. means for applying clock pulses to the gates of said transmission transistors for establishing transmission alternately; iv. through the feedback transmission transistors of the first and third stagEs and through said fourth transistor while preventing transmission through the remaining transmission transistors, and v. through the feedback transmission transistor of the second stage and through said fifth and sixth transistors while preventing transmission through the remaining transmission transistors.

Claim 5

An integrated circuit of enhancement-type MOS transistors comprising: a. three flip-flop stages interconnected to provide J-K capability; b. each said stage comprising a pair of series circuits for retaining binary logic levels; c. each said series circuit comprising a first enhancement-type MOS transistor to act as an inverter, and a second enhancement-type MOS transistor to act as a load connected in series with said inverter transistor, the resistance of said second transistor being higher than that of said first transistor; d. means directly connecting the common point between the transistors of a first of said series circuits in each of said stages to the gate of the inverter transistor of the other series circuit of the same stage; e. means including an enhancement-type MOS transistor to act as a feedback transmission transistor connecting the common point between the transistors of said other series circuit in each of said stages to the gate of the inverter transistor of the first series circuit of the same stage through said transmission transistor; f. interstage connecting means including: i. a fourth, enhancement-type MOS transistor to act as a transmission transistor connecting a common point between the transistors of said other series circuit of a first of said stages to the gate of the inverter transistor of the first series circuit of a second of said stages through said fourth transistor, ii. a fifth, enhancement-type MOS transistor to act as a transmission transistor connecting a common point between the transistors of said other series circuit of the second stage to the gate of the inverter transistor of the first series circuit of the third stage through said fifth transistor, iii. a sixth, enhancement-type MOS transistor to act as a transmission transistor connecting a common point between the transistors of the first series circuit of the second stage to the gate of the inverter transistor of said first series circuit of the first stage; and g. means for applying clock pulses to the gates of said transmission transistors for establishing transmission alternately; iv. through the feedback transmission transistors of the first and third stagEs and through said fourth transistor while preventing transmission through the remaining transmission transistors, and v. through the feedback transmission transistor of the second stage and through said fifth and sixth transistors while preventing transmission through the remaining transmission transistors.

Claim 6

An integrated circuit according to claim 3, including two further enhancement-type MOS transistors each connected in parallel with a respective one of the inverter transistors of said second stage, and set and reset input terminals each connected to the gate of a respective one of said further transistors.

Claim 7

An integrated circuit according to claim 4, including two still further enhancement-type MOS transistors each connected in series with the inverter transistor of a respective one of the series circuits of said first stage, and means connecting the gates of said still further transistors to respective terminals for receiving J and K inputs.