EP0746107A2
Expired / Lapsed
EP
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Programmable logic cell
Assignee: International Business Machines Corp
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Filing: 1996-05-07
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Granted: —
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Expires: 2016-05-07
Abstract
Abstract A programmable logic cell (70) has four logic gates, two of which are configurable. The two configurable logic gates (88a,b) are positioned near the logic cell inputs. Each configurable logic gate (88a,b) has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates (90a,b) receive the outputs (100a,b) of the configurable logic gates (88a,b). Four independent logic cell input nodes (84a-d) are provided, each having associated therewith a programmable input multiplexer (78a-d). Each input multiplexer (78a-d) can have inputs connected to at least two types of interconnect conductors (L1-L4,72a,74a). The cell (70) also has two output paths, each having associated therewith an independently-controlled output multiplexer (98a,b). The output (116a,b) of each output multiplexer (98a,b) is connected to an input (104a,b) of the other output multiplexer (98a,b). Additional features include a multiplexer (96) having inputs (o,p) connected to two cell input nodes (84b,c), a select input (M) connected to a third logic cell input node (84a), and an output connected to a cell output node (116a); a system low-skew data (e.g., clock) input clock available to at least one of the input multiplexers (78a-d); a flip-flop (92) connected within the logic cell (70); and internal cell feedback (112). The preferred method of programming utilizes user-programmed SRAM memory cells (M1-M28; Fig.10).
Inventors
- 👤 Allan Robert Bertolet
- 👤 Kim P.N. Clinton
- 👤 Christine Marie Fuller
- 👤 Scott Whitney Gould
- 👤 Steven Paul Hartman
- 👤 Joseph Andrew Iadanza
- 👤 Frank Ray Keyser
- 👤 Eric Ernest Millham
- 👤 Timothy Shawn Reny
- 👤 Brian A. Worth
- 👤 Gulson Yasar
- 👤 Terrance John Zittritsch
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 00:05
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1737
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
154 words
A programmable logic cell comprising: first and second logic gates, each of said first and second logic gates having at least two inputs, an output, and a control node, each of said first and second logic gates being configurable to perform one of a predetermined set of logic functions on logic signals supplied to its respective at least two inputs, each of said first and second logic gates being configured with its respective control node; and third and fourth logic gates, each of said third and fourth logic gates having first and second inputs, the first input of at least one of the third and fourth logic gates being connected to the output of the first logic gate, the second input of at least one of the third and fourth logic gates being connected to the output of the second logic gate, each of the third and fourth logic gates further having an output.
Claim 2
Dependent Claim
91 words
The programmable logic cell of claim 1 further comprising: a first multiplexer and a second multiplexer, wherein the first multiplexer has a first input connected to the output of the first logic gate, and a second input connected to the output of one of the third logic gate and the fourth logic gate, and wherein the second multiplexer has a first input connected to the output of the second logic gate, and a second input connected to the output of one of the third logic gate and the fourth logic gate.
Claim 3
Dependent Claim
70 words
The programmable logic cell of claim 1 further comprising: a first multiplexer having an output and a second multiplexer having an output, wherein the first multiplexer has a first input connected to the output of one of the first logic gate, the second logic gate, the third logic gate, and the fourth logic gate, the first multiplexer further having a second input connected to the output of the second multiplexer.
Claim 4
Dependent Claim
55 words
The programmable logic cell of claim 3 wherein the second multiplexer has a first input connected to the output of one of the first logic gate, the second logic gate, the third logic gate, and the fourth logic gate, the second multiplexer further having a second input connected to the output of the first multiplexer.
Claim 5
Dependent Claim
54 words
The programmable logic cell of claim 1 further comprising: a data storage circuit having an input connected to the output of the fourth logic gate, the data storage circuit further having an output; and an inverter having an input connected to the output of the third logic gate, the inverter further having an output.
Claim 6
Dependent Claim
109 words
The programmable logic cell of claim 5 further comprising: a first multiplexer having an output and a second multiplexer having an output, wherein the first multiplexer has a first input connected to the output of one of the first logic gate, the inverter, and the data storage circuit, the first multiplexer further having a second input connected to the output of the second multiplexer, and wherein the second multiplexer has a first input connected to the output of one of the second logic gate, the third logic gate and the fourth logic gate, the second multiplexer further having a second input connected to the output of the first multiplexer.
Claim 7
Dependent Claim
87 words
The programmable logic cell of claim 1 wherein the logic cell comprises a first cell input node, the logic cell further comprising: a first programmable inverter having an input connected to the first cell input node, an output connected to one of the two inputs of the first logic gate, and a control node such that a logic signal presented at the first cell input node may be controllably inverted or not before being passed to the one of the two inputs of the first logic gate.
Claim 8
Dependent Claim
114 words
The programmable logic cell of claim 7 wherein the logic cell comprises a second cell input node, the logic cell further comprising: a second programmable inverter having an input connected to the second cell input node, an output connected to one of the two inputs of the second logic gate, and a control node such that a logic signal presented at the second cell input node may be controllably inverted or not before being passed to the one of the two inputs of the second logic gate; and a single memory means connected to the control nodes of the first and second programmable inverters for commonly controlling both the first and second programmable inverters.
Claim 9
Dependent Claim
104 words
The programmable logic cell of claim 1 wherein the logic cell comprises four cell input nodes, the logic cell further comprising: a programmable inverter at each of said four cell input nodes, each programmable inverter having an input connected to its respective cell input node, an output connected to a respective different one of the inputs of the first and second logic gates, and a control node such that logic signals presented at any of the four cell input nodes may be controllably inverted or not before being passed to a respective different one of the inputs of the first and second logic gates.
Claim 10
Dependent Claim
50 words
The programmable logic cell of claim 1 wherein the output of each of the first and second logic gates comprises a commonly-connected output node, the commonly-connected output node comprising an output node for each of the predetermined set of logic functions of each of the first and second logic gates.
Claim 11
Dependent Claim
31 words
The programmable logic cell of claim 10 wherein the predetermined set of logic functions of each of the first and second logic gates comprises a NAND function and a NOR function.
Claim 12
Dependent Claim
31 words
The programmable logic cell of claim 1 wherein the predetermined set of logic functions of each of the first and second logic gates comprises a NAND function and a NOR function.
Claim 13
Dependent Claim
26 words
The programmable logic cell of claim 12 wherein the third logic gate comprises a NAND gate and wherein the fourth logic gate comprises an XNOR gate.
Claim 14
Dependent Claim
26 words
The programmable logic cell of claim 1 wherein the third logic gate comprises a NAND gate and wherein the fourth logic gate comprises an XNOR gate.
Claim 15
Dependent Claim
91 words
The programmable logic cell of claim 1 wherein the logic cell comprises at least three cell inputs, the logic cell further comprising: a multiplexer having first and second inputs and a control input, the first input of the multiplexer being connected to a first one of the at least three cell inputs, the second input of the multiplexer being connected to a second one of the at least three cell inputs, and the control input of the multiplexer being connected to a third one of the at least three cell inputs.
Claim 16
Dependent Claim
38 words
The programmable logic cell of claim 1 wherein the logic cell further comprises: a single memory means connected to the control nodes of the first and second logic gates for commonly configuring the first and second logic gates.
Claim 17
Dependent Claim
18 words
A field programmable gate array having a plurality of programmable logic cells as set forth in claim 1.
References Cited (Backward Citations)
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