US5500609A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wildcard addressing structure for configurable cellular array
Assignee: Xilinx Inc
•
Filing: 1995-06-06
•
Granted: 1996-03-19
•
Expires: 2015-06-06
Abstract
Abstract An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowing memory bits to be addressed both individually and in large and arbitrary groups are disclosed. Further a control store for configuring the FPGA is addressed as an SRAM and can be dynamically reconfigured during operation.
Inventors
- 👤 Thomas A. Kean
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:46
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/34; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1737; H03K19/177; H03K19/17704; H03K19/17748; H03K19/17752; H03K19/17756; H03K19/17758
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
113 words
A logic structure comprising: an array of memory cells arranged in rows and columns; a plurality of decoders, one decoder for each row or each column, each decoder receiving both true and complemented values for each address bit; a pair of logic gates associated with each address bit, wherein said pair of logic gates provide said true and complemented values for each address bit; and a wildcard register providing one enable bit for each address bit, wherein both of said logic gates receive said enable bit from said wildcard register, one of said logic gates receives said address bit, and the other of said logic gates receives the complement of said address bit.
Claim 2
Dependent Claim
113 words
A logic structure comprising: an array of memory cells arranged in rows and columns; a plurality of decoders, one decoder for each row or each column, each decoder receiving both true and complemented values for each address bit; a pair of logic gates associated with each address bit, wherein said pair of logic gates provide said true and complemented values for each address bit; and a wildcard register providing one enable bit for each address bit, wherein both of said logic gates receive said enable bit from said wildcard register, one of said logic gates receives said address bit, and the other of said logic gates receives the complement of said address bit.
Claim 3
Independent Claim
134 words
A method of simultaneously writing a plurality of cells comprising the steps of: arranging a plurality of memory cells in rows and columns; providing a decoder for each row or each column, each decoder receiving both true and complemented values for each address bit; providing a pair of logic gates for each address bit, wherein said pair of logic gates provide said true and complemented values for each address bit; and placing a wildcard register in operative relation to said pair of logic gates, wherein said wildcard register provides one enable bit for each address bit, further wherein both of said logic gates receive said enable bit from said wildcard register, one of said logic gates receives said address bit, and the other of said logic gates receives the complement of said address bit.
Claim 4
Independent Claim
134 words
A method of simultaneously writing a plurality of cells comprising the steps of: arranging a plurality of memory cells in rows and columns; providing a decoder for each row or each column, each decoder receiving both true and complemented values for each address bit; providing a pair of logic gates for each address bit, wherein said pair of logic gates provide said true and complemented values for each address bit; and placing a wildcard register in operative relation to said pair of logic gates, wherein said wildcard register provides one enable bit for each address bit, further wherein both of said logic gates receive said enable bit from said wildcard register, one of said logic gates receives said address bit, and the other of said logic gates receives the complement of said address bit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-19 | 1999-09-18 | 2000-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-19 | 2003-09-18 | 2004-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-19 | 2007-09-18 | 2008-03-19 | $7700.00 | Window Closed / Lapsed |