US5303181A
Expired / Lapsed
US
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Programmable chip enable logic function
Assignee: Harris Corp
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Filing: 1992-10-20
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Granted: 1994-04-12
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Expires: 2012-10-20
Abstract
Abstract A programmable chip enable provides for enabling or disabling an integrated circuit in response to a selected one of a plurality of logic signals. In a specific application, the programmable enable function is used in combination with a plurality of field programmable memory devices. The enable functions of the respective devices are programmed to prevent simultaneous enablement of the memory devices which have their outputs connected together.
Inventors
- 👤 David W. Stockton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:06
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; G; G11; G11C; G11C17/00; G11C17/14; G11C17/18; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
184 words
A memory circuit arrangement, comprising: a first memory device having an array of memory elements, a plurality of inputs and outputs for accessing the memory elements, an input for receiving first and second enable signals from an external source, and programmable circuit means for selectively enabling the first memory device in response to one of said first and second enable signals; and a second memory device having an array of memory elements, a plurality of inputs and outputs for accessing the memory elements, an input for receiving said first and second enable signals from said external source, and programmable circuit means for selectively enabling the second memory device in response to the other of said first and second enable signals; and wherein, at least one of the respective outputs of said first and second memory devices are connected together; wherein said programmable circuit means comprises a logic element having a first input connected to said input for receiving logic level signals from said external source, a second input connected to a reference voltage by a programmable element, and means for programming said programmable element.
Claim 2
Dependent Claim
184 words
A memory circuit arrangement, comprising: a first memory device having an array of memory elements, a plurality of inputs and outputs for accessing the memory elements, an input for receiving first and second enable signals from an external source, and programmable circuit means for selectively enabling the first memory device in response to one of said first and second enable signals; and a second memory device having an array of memory elements, a plurality of inputs and outputs for accessing the memory elements, an input for receiving said first and second enable signals from said external source, and programmable circuit means for selectively enabling the second memory device in response to the other of said first and second enable signals; and wherein, at least one of the respective outputs of said first and second memory devices are connected together; wherein said programmable circuit means comprises a logic element having a first input connected to said input for receiving logic level signals from said external source, a second input connected to a reference voltage by a programmable element, and means for programming said programmable element.
Claim 3
Dependent Claim
14 words
An integrated circuit according to claim 1, wherein said programmable element is a fuse.
Claim 4
Dependent Claim
63 words
An integrated circuit according to claim 1, wherein said means for programming said programmable element comprises an inverter having an input connected to the programmable element and having an output, and a NAND gate having a first input connected to the output of the inverter, a second input connected to a programming control signal source, and an output connected to the programmable element.
Claim 5
Dependent Claim
16 words
An integrated circuit according to claim 1, wherein said logic element is an Exclusive OR gate.
Claim 6
Dependent Claim
159 words
A field programmable memory device, comprising: a first array of memory elements; a second array of memory elements; a plurality of inputs and outputs for accessing the memory elements in each of the arrays; an enable input for receiving first and second enable signals from an external source; and programmable circuit means for selectively enabling the first array of memory elements in response to one of said first and second enable signals and for selectively enabling the second array of memory elements in response to the other of said first and second enable signals; wherein at least one of the respective outputs of the first and second arrays of memory elements are connected together; wherein said programmable circuit means comprises a logic element having a first input connected to said input for receiving logic level signals from said external source, a second input connected to a reference voltage by a programmable element, and means for programming said programmable element.
Claim 7
Dependent Claim
159 words
A field programmable memory device, comprising: a first array of memory elements; a second array of memory elements; a plurality of inputs and outputs for accessing the memory elements in each of the arrays; an enable input for receiving first and second enable signals from an external source; and programmable circuit means for selectively enabling the first array of memory elements in response to one of said first and second enable signals and for selectively enabling the second array of memory elements in response to the other of said first and second enable signals; wherein at least one of the respective outputs of the first and second arrays of memory elements are connected together; wherein said programmable circuit means comprises a logic element having a first input connected to said input for receiving logic level signals from said external source, a second input connected to a reference voltage by a programmable element, and means for programming said programmable element.
Claim 8
Dependent Claim
14 words
An integrated circuit according to claim 5, wherein said programmable element is a fuse.
Claim 9
Dependent Claim
63 words
An integrated circuit according to claim 5, wherein said means for programming said programmable element comprises an inverter having an input connected to the programmable element and having an output, and a NAND gate having a first input connected to the output of the inverter, a second input connected to a programming control signal source, and an output connected to the programmable element.
Claim 10
Dependent Claim
16 words
An integrated circuit according to claim 5, wherein said logic element is an Exclusive OR gate.
Claim 11
Dependent Claim
141 words
A memory circuit arrangement, comprising: a first memory device having an array of memory elements, a plurality of inputs and outputs for accessing the memory elements, an input for receiving first and second enable signals from an external source, and electrically programmable circuit means for selectively enabling the first memory device in response to one of said first and second enable signals; and a second memory device having an array of memory elements, a plurality of inputs and outputs for accessing the memory elements, an input for receiving said first and second enable signals from said external source, and electrically programmable circuit means for selectively enabling the second memory device in response to the other of said first and second enable signals; and wherein, at least one of the respective outputs of said first and second memory devices are connected together.
Claim 12
Dependent Claim
141 words
A memory circuit arrangement, comprising: a first memory device having an array of memory elements, a plurality of inputs and outputs for accessing the memory elements, an input for receiving first and second enable signals from an external source, and electrically programmable circuit means for selectively enabling the first memory device in response to one of said first and second enable signals; and a second memory device having an array of memory elements, a plurality of inputs and outputs for accessing the memory elements, an input for receiving said first and second enable signals from said external source, and electrically programmable circuit means for selectively enabling the second memory device in response to the other of said first and second enable signals; and wherein, at least one of the respective outputs of said first and second memory devices are connected together.
Claim 13
Dependent Claim
115 words
A field programmable memory device, comprising: a first array of memory elements; a second array of memory elements; a plurality of inputs and outputs for accessing the memory elements in each of the arrays; an enable input for receiving first and second enable signals from an external source; and electrically programmable circuit means for selectively enabling the first array of memory elements in response to one of said first and second enable signals and for selectively enabling the second array of memory elements in response to the other of said first and second enable signals; wherein at least one of the respective outputs of the first and second arrays of memory elements are connected together.
Claim 14
Dependent Claim
115 words
A field programmable memory device, comprising: a first array of memory elements; a second array of memory elements; a plurality of inputs and outputs for accessing the memory elements in each of the arrays; an enable input for receiving first and second enable signals from an external source; and electrically programmable circuit means for selectively enabling the first array of memory elements in response to one of said first and second enable signals and for selectively enabling the second array of memory elements in response to the other of said first and second enable signals; wherein at least one of the respective outputs of the first and second arrays of memory elements are connected together.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-11 | 1997-10-11 | 1998-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-11 | 2001-10-11 | 2002-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-11 | 2005-10-11 | 2006-04-12 | $7700.00 | Window Closed / Lapsed |