Programmable chip enable logic function

Claim 2

An integrated circuit having a programmable chip enable, comprising: at least one data input; at least one data output; an enable input for receiving at least one of a relatively high logic level signal and a relatively low logic level signal from an external source; and programmable circuit means, connected to said enable input, for enabling the integrated circuit to produce an output signal at said data output in response to a selected one of said relatively high and said relatively low logic level signals received at said enable input, and for disabling the integrated circuit to prevent an output signal from being produced at the data output in response to the other of said signals received at the enable input.

Claim 3

An integrated circuit according to claim 1, wherein said programmable circuit means comprises a logic element having a first input connected to said input for receiving logic level signals from said external source, a second input connected to a reference voltage by a programmable element, and means for programming said programmable element.

Claim 4

An integrated circuit according to claim 2, wherein said programmable element is a fuse.

Claim 5

An integrated circuit according to claim 2, wherein said means for programming said programmable element comprises an inverter having an input connected to the programmable element and having an output, and a NAND gate having a first input connected to the output of the inverter, a second input connected to a programming control signal source, and an output connected to the programmable element.

Claim 6

An integrated circuit according to claim 2, wherein said logic element is an Exclusive OR gate.

Claim 7

A field programmable memory device having a programmable chip enable, comprising: an array of memory elements; a plurality of inputs and outputs for accessing the memory elements; an enable input for receiving at least one of a relatively high logic level signal and a relatively low logic level signal from an external source; and programmable circuit means, connected to said enable input for receiving logic level signals, for enabling the memory device in response to a selected one of said relatively high and said relatively low logic level signals received at said enable input; wherein said programmable circuit means has a programming input, connected to a programming control signal source, for receiving a programming control signal to program the programmable circuit means to respond to said selected one of said relatively high and low logic level signals received at said enable input.

Claim 8

A field programmable memory device having a programmable chip enable, comprising: an array of memory elements; a plurality of inputs and outputs for accessing the memory elements; an enable input for receiving at least one of a relatively high logic level signal and a relatively low logic level signal from an external source; and programmable circuit means, connected to said enable input for receiving logic level signals, for enabling the memory device in response to a selected one of said relatively high and said relatively low logic level signals received at said enable input; wherein said programmable circuit means has a programming input, connected to a programming control signal source, for receiving a programming control signal to program the programmable circuit means to respond to said selected one of said relatively high and low logic level signals received at said enable input.

Claim 9

A field programmable memory device according to claim 6, wherein said programmable circuit means comprises a logic element having a first input connected to said input for receiving logic level signals from an external source, a second input connected to a reference voltage by a programmable element, and means for programming said programmable element.

Claim 10

A field programmable memory device according to claim 7, wherein said programmable element is a fuse.

Claim 11

A field programmable memory device according to claim 7, wherein said means for programming said programmable element comprises an inverter having an input connected to the programmable element and having an output, and a NAND gate having a first input connected to the output of the inverter, a second input connected to the programming input, and an output connected to the programmable element.

Claim 12

A field programmable memory device according to claim 7, wherein said logic element is an Exclusive OR gate.

Claim 13

An integrated circuit device, comprising: a circuit having at least one input and at least one output, and having an enable input; an enabling circuit having an input connected to an input pin of the integrated circuit device for receiving at least one of a relatively high logic level signal and a relatively low logic level signal from an external source, and having an output connected to the enable input of the circuit, and having a programming input connected to a programming control signal source; and programmable means in said enabling circuit for causing the enabling circuit to provide an enabling signal to the enabling input of the circuit in response to a selected one of said relatively high and said relatively low logic level signals.

Claim 14

An integrated circuit device, comprising: a circuit having at least one input and at least one output, and having an enable input; an enabling circuit having an input connected to an input pin of the integrated circuit device for receiving at least one of a relatively high logic level signal and a relatively low logic level signal from an external source, and having an output connected to the enable input of the circuit, and having a programming input connected to a programming control signal source; and programmable means in said enabling circuit for causing the enabling circuit to provide an enabling signal to the enabling input of the circuit in response to a selected one of said relatively high and said relatively low logic level signals.

Claim 15

An integrated circuit device according to claim 11, wherein said programmable means comprises a logic element having a first input connected to the input pin of the integrated circuit device, a second input connected to a reference voltage by a programmable element, and means for programming said programmable element.

Claim 16

An integrated circuit device according to claim 12, wherein said means for programming said programmable element comprises an inverter having an input connected to the programmable element and having an output, and a NAND gate having a first input connected to the output of the inverter, a second input connected to the programming input, and an output connected to the programmable element.

Claim 17

An integrated circuit device according to claim 12, wherein said logic element is an Exclusive OR gate.

Claim 18

A field programmable memory device, comprising: an array of memory elements; a plurality of inputs and outputs for accessing the memory elements; an enable input for receiving a signal which enables the memory device; an enabling circuit having an input connected to an input pin of the memory device for receiving at least one of a relatively high logic level signal and a relatively low logic level signal from an external source, and having an output connected to the enable input of the memory device, and having a programming input connected to a programming control signal source; and programmable means in said enabling circuit for causing the enabling circuit to provide the enabling signal to the enabling input in response to a selected one of said relatively high and said relatively low logic level signals.

Claim 19

A field programmable memory device, comprising: an array of memory elements; a plurality of inputs and outputs for accessing the memory elements; an enable input for receiving a signal which enables the memory device; an enabling circuit having an input connected to an input pin of the memory device for receiving at least one of a relatively high logic level signal and a relatively low logic level signal from an external source, and having an output connected to the enable input of the memory device, and having a programming input connected to a programming control signal source; and programmable means in said enabling circuit for causing the enabling circuit to provide the enabling signal to the enabling input in response to a selected one of said relatively high and said relatively low logic level signals.

Claim 20

A field programmable memory device according to claim 15, wherein said programmable means comprises a logic element having a first input connected to the input pin of the memory device, a second input connected to a reference voltage by a programmable element, and means for programming said programmable element.

Claim 21

A field programmable memory device according to claim 16, wherein said means for programming said programmable element comprises an inverter having an input connected to the programmable element and having an output, and a NAND gate having a first input connected to the output of the inverter, a second input connected to the programming input, and an output connected to the programmable element.

Claim 22

A field programmable memory device according to claim 16, wherein said logic element is an Exclusive OR gate.

Claim 23

A programmable chip enable for an integrated circuit, comprising: an input for receiving at least one of a relatively high logic level signal and a relatively low logic level signal from an external source; and programmable circuit means, connected to said input, for enabling the integrated circuit in response to a selected one of said relatively high and said relatively low logic level signals received at said input; wherein said programmable circuit means comprises a logic element having a first input connected to said input for receiving logic level signals from said external source, a second input connected to a reference voltage by a programmable element, and means for programming said programmable element; and wherein said means for programming said programmable element comprises an inverter having an input connected to the programmable element and having an output, and a NAND gate having a first input connected to the output of the inverter, a second input connected to a programming control signal source, and an output connected to the programmable element.

Claim 24

A programmable chip enable for an integrated circuit, comprising: an input for receiving at least one of a relatively high logic level signal and a relatively low logic level signal from an external source; and programmable circuit means, connected to said input, for enabling the integrated circuit in response to a selected one of said relatively high and said relatively low logic level signals received at said input; wherein said programmable circuit means comprises a logic element having a first input connected to said input for receiving logic level signals from said external source, a second input connected to a reference voltage by a programmable element, and means for programming said programmable element; and wherein said means for programming said programmable element comprises an inverter having an input connected to the programmable element and having an output, and a NAND gate having a first input connected to the output of the inverter, a second input connected to a programming control signal source, and an output connected to the programmable element.

Claim 25

A field programmable memory device comprising: an array of memory elements; a plurality of inputs and outputs for accessing the memory elements; an input for receiving at least one of a relatively high logic level signal and a relatively low logic level signal from an external source; and programmable circuit means, connected to said input for receiving logic level signals, for enabling the memory device in response to a selected one of said relatively high and said relatively low logic level signals received at said input; wherein said programmable circuit means comprises a logic element having a first input connected to said input for receiving logic level signals from an external source, a second input connected to a reference voltage by a programmable element, and means for programming said programmable element; and wherein said means for programming said programmable element comprises an inverter having an input connected to the programmable element and having an output, and a NAND gate having a first input connected to the output of the inverter, a second input connected to a programming control signal source, and an output connected to the programmable element.

Claim 26

A field programmable memory device comprising: an array of memory elements; a plurality of inputs and outputs for accessing the memory elements; an input for receiving at least one of a relatively high logic level signal and a relatively low logic level signal from an external source; and programmable circuit means, connected to said input for receiving logic level signals, for enabling the memory device in response to a selected one of said relatively high and said relatively low logic level signals received at said input; wherein said programmable circuit means comprises a logic element having a first input connected to said input for receiving logic level signals from an external source, a second input connected to a reference voltage by a programmable element, and means for programming said programmable element; and wherein said means for programming said programmable element comprises an inverter having an input connected to the programmable element and having an output, and a NAND gate having a first input connected to the output of the inverter, a second input connected to a programming control signal source, and an output connected to the programmable element.

Claim 27

A field programmable memory device having a programmable chip enable, comprising: an array of memory elements; a plurality of inputs and outputs for accessing the memory elements; an enable input for receiving at least one of a relatively high logic level signal and a relatively low logic level signal from an external source; and programmable circuit means, connected to said enable input for receiving logic level signals, for enabling the memory device to provide access to the memory elements in response to a selected one of said relatively high and said relatively low logic level signals received at said enable input, and for disabling the memory device to prevent access to the memory elements in response to the other of said signals received at the enable input.

Claim 28

A field programmable memory device having a programmable chip enable, comprising: an array of memory elements; a plurality of inputs and outputs for accessing the memory elements; an enable input for receiving at least one of a relatively high logic level signal and a relatively low logic level signal from an external source; and programmable circuit means, connected to said enable input for receiving logic level signals, for enabling the memory device to provide access to the memory elements in response to a selected one of said relatively high and said relatively low logic level signals received at said enable input, and for disabling the memory device to prevent access to the memory elements in response to the other of said signals received at the enable input.