Abstract The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a generally rectangular matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical rows of logic cells. The array further includes at least one horizontally aligned express bus running between adjacent rows of logic cells, the logic cells in the adjacent rows being connectable thereto, and at least one vertically aligned express bus running between adjacent columns of logic cells, the logic cells in the adjacent columns being connectable thereto. The array further includes a plurality of logic cell I/O pins located at the periphery of the matrix and connectable to the logic cells in the rows and columns at the periphery of the matrix. Furthermore, the array includes a plurality of express bus I/O pins directly connectable to the express busses.
In a configurable logic array that includes a plurality of individually configurable logic cells arranged in a generally rectangular matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical rows of logic cells, the array further including at least one horizontally aligned express bus running between adjacent rows of logic cells, said logic cells in said adjacent rows being connectable thereto, and at least one vertically aligned express bus running between adjacent columns of logic cells, said logic cells in said adjacent columns being connectable thereto, the array further including a plurality of logic cells I/O pins located at the periphery of the matrix and connectable to the logic cells in the rows and columns at the periphery of the matrix, the improvement comprising a plurality of express bus I/O pins directly connectable to the express busses.
Claim 2
Dependent Claim
143 words
In a configurable logic array that includes a plurality of individually configurable logic cells arranged in a generally rectangular matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical rows of logic cells, the array further including at least one horizontally aligned express bus running between adjacent rows of logic cells, said logic cells in said adjacent rows being connectable thereto, and at least one vertically aligned express bus running between adjacent columns of logic cells, said logic cells in said adjacent columns being connectable thereto, the array further including a plurality of logic cells I/O pins located at the periphery of the matrix and connectable to the logic cells in the rows and columns at the periphery of the matrix, the improvement comprising a plurality of express bus I/O pins directly connectable to the express busses.