Abstract Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal. For each bit, a carry propagate signal is generated by a lookup table programmable function generator and is used by dedicated hardware to generate the carry signal.
A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: means for generating a first input value (B i ); an input terminal for providing a second input value (A i ); a carry-in terminal (C i ) and a carry-out terminal (C i+1 ); a multiplexer (923) for connecting one of said input terminal and said carry-in terminal to said carry-out terminal; and a lookup table (903) for generating a propagate signal causing said multiplexer to connect said input terminal to said carry-out terminal when and only when said first input value is equal to said second input value (A i =B i ), and to connect said carry-in terminal to said carry-out terminal when and only when said first input value is not equal to said second input value (A i ≠B i ).
Claim 2
Dependent Claim
145 words
A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: means for generating a first input value (B i ); an input terminal for providing a second input value (A i ); a carry-in terminal (C i ) and a carry-out terminal (C i+1 ); a multiplexer (923) for connecting one of said input terminal and said carry-in terminal to said carry-out terminal; and a lookup table (903) for generating a propagate signal causing said multiplexer to connect said input terminal to said carry-out terminal when and only when said first input value is equal to said second input value (A i =B i ), and to connect said carry-in terminal to said carry-out terminal when and only when said first input value is not equal to said second input value (A i ≠B i ).
Claim 3
Dependent Claim
50 words
A programmable logic device as in claim 1 further comprising: function generating means (904) which receives as input said propagate signal and a signal on said carry-in terminal, said function generating means being capable of generating the XOR function of said propagate signal and said signal on said carry-in terminal.
Claim 4
Dependent Claim
19 words
A programmable logic device as in claim 2 in which said function generating means (904) is an XOR gate.
Claim 5
Dependent Claim
48 words
A programmable logic device as in claim 1 in which two adjacent ones of said logic blocks calculate the sum and carry of said input values, that logic block for calculating the sum comprising a look-up table (904) capable of generating all functions of at least two inputs.
Claim 6
Dependent Claim
55 words
A programmable logic device as in claim 1 in which said means for generating a first input value (B i ) comprises a plurality of inputs to said lookup table in combination with a function stored in said lookup table which provides said first input value as a user-selected function of said plurality of inputs.
Claim 7
Dependent Claim
34 words
A programmable logic device as in claim 1 in which said means for generating a first input value (B i ) comprises an input to said lookup table which carries said first input value.