Logic structure and circuit for fast carry

Claim 2

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and further comprising: means for disconnecting said first input terminal from said carry-out terminal, said means for disconnecting being controllable to disconnect said first input terminal from said carry-out terminal independent of the states of said signals on said first and second input terminals; and means for applying an alternative signal to said carry-out terminal when said means for disconnecting is disconnecting.

Claim 3

A programmable logic device as in claim 1 further comprising: a third input terminal; means for selecting said alternative signal from a stored value and a signal on said third input terminal.

Claim 4

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and further comprising: a third input terminal; means for providing a signal on said third input terminal; means for selecting between causing said first switching means to connect said first input terminal to said carry-out terminal and causing said first switching means to apply said signal on said third terminal to said carry-out terminal.

Claim 5

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and further comprising: a third input terminal; means for providing a signal on said third input terminal; means for selecting between causing said first switching means to connect said first input terminal to said carry-out terminal and causing said first switching means to apply said signal on said third terminal to said carry-out terminal.

Claim 6

A programmable logic device as in claim 3 further comprising means for selecting between applying a stored value to said carry-out terminal and applying an input signal to said carry-out terminal.

Claim 7

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and further comprising: means for inverting or not inverting a signal to generate an operand; and means for applying said operand to said second input terminal.

Claim 8

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and further comprising: means for inverting or not inverting a signal to generate an operand; and means for applying said operand to said second input terminal.

Claim 9

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and further comprising: an XNOR gate; a first inverter and a second inverter; third and fourth switching means; and a first memory cell and a second memory cell, each having an output and an output-complement; wherein said first input terminal and said second input terminal are inputs to said XNOR gate, an output of said XNOR gate is input to said first inverter by said third switching means; the output of said first inverter is input to said second inverter; said output-complement of said first memory cell is input to said first inverter by said fourth controllable switching means, said first switching means is controlled by the output signal of said second inverter, said second switching means is controlled by said output signal of said first inverter, said third switching means is controlled by said output of said second memory cell, said fourth controllable switching means is controlled by said output-complement of said second memory cell.

Claim 10

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and further comprising: an XNOR gate; a first inverter and a second inverter; third and fourth switching means; and a first memory cell and a second memory cell, each having an output and an output-complement; wherein said first input terminal and said second input terminal are inputs to said XNOR gate, an output of said XNOR gate is input to said first inverter by said third switching means; the output of said first inverter is input to said second inverter; said output-complement of said first memory cell is input to said first inverter by said fourth controllable switching means, said first switching means is controlled by the output signal of said second inverter, said second switching means is controlled by said output signal of said first inverter, said third switching means is controlled by said output of said second memory cell, said fourth controllable switching means is controlled by said output-complement of said second memory cell.

Claim 11

A programmable logic device as in claim 6 in which said memory cells are static random access memory cells.

Claim 12

A programmable logic device as in claim 6 in which said memory cells are electrically programmable switches.

Claim 13

A programmable logic device as in claim 8 in which said electrically programmable switches are electrically erasable.

Claim 14

A programmable logic device as in claim 6 in which said memory cells are fuses.

Claim 15

A programmable logic device as in claim 6 in which said memory cells are antifuses.

Claim 16

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and further comprising a three-way multiplexer for selecting between causing said first switching means to connect said first input terminal to said carry-out terminal, causing said first switching means to connect a third input terminal to said carry-out terminal, and causing said first switching means to apply a stored value to said carry-out terminal.

Claim 17

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and further comprising a three-way multiplexer for selecting between causing said first switching means to connect said first input terminal to said carry-out terminal, causing said first switching means to connect a third input terminal to said carry-out terminal, and causing said first switching means to apply a stored value to said carry-out terminal.

Claim 18

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and further comprising: a third input terminal; means for providing a stored value; third, fourth, fifth, and sixth controllable switching means; and means for controlling said third, fourth, fifth and sixth controllable switching means such that: said third input terminal is coupled to said carry-out terminal only when said first, third, and fifth switching means are conductive; said stored value is coupled to said carry-out terminal only when said sixth and said first switching means are conductive; and said first input terminal is coupled to said carry-out terminal only when said fourth and first switching means are conductive.

Claim 19

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and further comprising: a third input terminal; means for providing a stored value; third, fourth, fifth, and sixth controllable switching means; and means for controlling said third, fourth, fifth and sixth controllable switching means such that: said third input terminal is coupled to said carry-out terminal only when said first, third, and fifth switching means are conductive; said stored value is coupled to said carry-out terminal only when said sixth and said first switching means are conductive; and said first input terminal is coupled to said carry-out terminal only when said fourth and first switching means are conductive.

Claim 20

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; in which said means for causing comprises: an XNOR gate having two input terminals coupled respectively to said first and second input terminals, and an output terminal; a first inverter, the output of said first inverter controlling said second switching means; means for providing a stored value; third switching means, wherein said third switching means selects between providing said stored value and a signal output from said XNOR gate to the input terminal of said first inverter; and a second inverter connected to the output terminal of said first inverter, the output terminal of said second inverter controlling said first switching means.

Claim 21

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; in which said means for causing comprises: an XNOR gate having two input terminals coupled respectively to said first and second input terminals, and an output terminal; a first inverter, the output of said first inverter controlling said second switching means; means for providing a stored value; third switching means, wherein said third switching means selects between providing said stored value and a signal output from said XNOR gate to the input terminal of said first inverter; and a second inverter connected to the output terminal of said first inverter, the output terminal of said second inverter controlling said first switching means.

Claim 22

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and further comprising: an XNOR gate; a first memory cell and second memory cell; a first multiplexer with at least two inputs and one output; a third input terminal; wherein the output of said first memory cell is an input of said first multiplexer; said third input terminal is an input of said first multiplexer; the output of said second memory cell selects between connecting said first memory cell and connecting said third input terminal to said output terminal of said first multiplexer; the output of said first multiplexer is an input of said XNOR gate; said second input terminal is coupled to an input of said XNOR gate; said second input terminal is coupled to an input of said XNOR gate; and said XNOR gate and said first input terminal control said means for causing.

Claim 23

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and further comprising: an XNOR gate; a first memory cell and second memory cell; a first multiplexer with at least two inputs and one output; a third input terminal; wherein the output of said first memory cell is an input of said first multiplexer; said third input terminal is an input of said first multiplexer; the output of said second memory cell selects between connecting said first memory cell and connecting said third input terminal to said output terminal of said first multiplexer; the output of said first multiplexer is an input of said XNOR gate; said second input terminal is coupled to an input of said XNOR gate; said second input terminal is coupled to an input of said XNOR gate; and said XNOR gate and said first input terminal control said means for causing.

Claim 24

An ordered array of logic blocks each comprising at least one array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; wherein said carry-out terminal of a second logic block is coupled to at least said carry-in terminal of a first logic block preceding said second logic block and to said carry-in terminal of a third logic block following said second logic block, and in which said logic blocks are positioned in a rectangular array of horizontal rows and vertical columns and in which said first logic block and said third logic block are positioned in one of the same column as said second logic block and the same row as said second logic block.

Claim 25

An ordered array of logic blocks each comprising at least one array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; wherein said carry-out terminal of a second logic block is coupled to at least said carry-in terminal of a first logic block preceding said second logic block and to said carry-in terminal of a third logic block following said second logic block, and in which said logic blocks are positioned in a rectangular array of horizontal rows and vertical columns and in which said first logic block and said third logic block are positioned in one of the same column as said second logic block and the same row as said second logic block.

Claim 26

An ordered array of logic blocks as in claim 16 in which said first logic block and said third logic block are contiguous to said second logic block.

Claim 27

An integrated circuit structure comprising: an array of configurable logic blocks, said configurable logic blocks each including means for calculating a selectable one of a plurality of functions of a plurality of input signals, including at least a sum function and another function having a truth table different from the sum function; and dedicated hardware for performing the carry function, said dedicated hardware including means for receiving at least some of said plurality of input signals; means for receiving a carry-in signal; means for providing a carry-out signal; and means for calculating said carry function from said carry-in signal and some of said plurality of input signals, and generating said carry-out signal.

Claim 28

An integrated circuit structure comprising: an array of configurable logic blocks, said configurable logic blocks each including means for calculating a selectable one of a plurality of functions of a plurality of input signals, including at least a sum function and another function having a truth table different from the sum function; and dedicated hardware for performing the carry function, said dedicated hardware including means for receiving at least some of said plurality of input signals; means for receiving a carry-in signal; means for providing a carry-out signal; and means for calculating said carry function from said carry-in signal and some of said plurality of input signals, and generating said carry-out signal.

Claim 29

An integrated circuit structure as in claim 18 further comprising: dedicated interconnect lines for interconnecting said hardware for performing the carry function in a first logic block to hardware for performing the carry function in at least a second logic block.

Claim 30

An integrated circuit structure as in claim 19 in which said dedicated interconnect lines further comprise lines for interconnecting said hardware for performing the carry function in a first logic block to hardware for performing the carry function in at least a third logic block.

Claim 31

An integrated circuit structure comprising: programmable interconnect lines; an array of configurable logic blocks, said configurable logic blocks each including means for calculating a selectable function of a plurality of input signals, including at least a sum function and another function; and dedicated hardware for performing the carry function, comprising: means for receiving at least some of said plurality of input signals; a carry-out terminal; means for generating a carry-out signal in response to a carry-in signal on said carry-in terminal and input signals on selected ones of said programmable interconnect lines, and placing said carry-out signal on said carry-out terminal; and means for selecting said carry-in signal of said third logic block from among at least carry-out signals on said carry-out terminals of said first and second logic blocks.

Claim 32

An integrated circuit structure comprising: programmable interconnect lines; an array of configurable logic blocks, said configurable logic blocks each including means for calculating a selectable function of a plurality of input signals, including at least a sum function and another function; and dedicated hardware for performing the carry function, comprising: means for receiving at least some of said plurality of input signals; a carry-out terminal; means for generating a carry-out signal in response to a carry-in signal on said carry-in terminal and input signals on selected ones of said programmable interconnect lines, and placing said carry-out signal on said carry-out terminal; and means for selecting said carry-in signal of said third logic block from among at least carry-out signals on said carry-out terminals of said first and second logic blocks.

Claim 33

An integrated circuit structure as in claim 21 in which said logic blocks are located in rows and columns within said integrated circuit structure, and said third logic block is positioned contiguous to said first and second logic blocks.

Claim 34

An integrated circuit structure as in claim 22 in which said first logic block is positioned to the left of said third logic block and said second logic block is positioned below said third logic block.

Claim 35

An integrated circuit structure as in claim 22 in which said first logic block is positioned to the left of said third logic block and said second logic block is positioned above said third logic block.

Claim 36

An integrated circuit structure as in claim 22 in which said first logic block is positioned above said third logic block and said second logic block is positioned below said third logic block.

Claim 37

An integrated circuit structure as in claim 21 in which said logic blocks are positioned in rows and columns and said first and second logic blocks are located in the same row or same column as said third logic block.

Claim 38

An array of configurable logic blocks, each logic block comprising: two stages, each stage comprising: at least a first input terminal and a second input terminal; a carry-in terminal; a carry-out terminal; dedicated circuitry for performing carry logic with at least three inputs and at least one output; wherein three of said at least three inputs comprise: a signal on said first input terminal; a signal on said second input terminal; and a signal on said carry-in terminal; and wherein said output is a carry function of said three inputs; said carry-out terminal of said first stage being connected directly to said carry-in terminal of said second stage, and said carry-out terminal of said second stage being connected through buffering means to said carry-in terminal of another one of said logic blocks; and controllable means for substituting for said carry-out signal a stored signal to said carry-out terminal.

Claim 39

An array of configurable logic blocks, each logic block comprising: two stages, each stage comprising: at least a first input terminal and a second input terminal; a carry-in terminal; a carry-out terminal; dedicated circuitry for performing carry logic with at least three inputs and at least one output; wherein three of said at least three inputs comprise: a signal on said first input terminal; a signal on said second input terminal; and a signal on said carry-in terminal; and wherein said output is a carry function of said three inputs; said carry-out terminal of said first stage being connected directly to said carry-in terminal of said second stage, and said carry-out terminal of said second stage being connected through buffering means to said carry-in terminal of another one of said logic blocks; and controllable means for substituting for said carry-out signal a stored signal to said carry-out terminal.

Claim 40

An array as in claim 27 further comprising: controllable means for selectively propagating said signal on said carry-in terminal to said carry-out terminal; or propagating said signal on one of said first input terminal and said second input terminal to said carry-out terminal.

Claim 41

An array as in claim 27 further comprising: a third input terminal; controllable means for selectively propagating a signal on said third input terminal to said carry-out terminal.

Claim 42

An array as in claim 27 further comprising: controllable means for selectively propagating said signal on said carry-in terminal to said carry-out terminal independent of signals on said first and second input terminals.

Claim 43

An array as in claim 27 further comprising: second means for computing the carry function of said signal on said first input terminal, said signal on said carry-in terminal, and a complement of said signal on said second input terminal; and means for selecting between using said at least one circuit or said at least one stage and using said second means.

Claim 44

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and further comprising: means for receiving a first input signal and placing said first input signal on said first input terminal; means for receiving a second input signal; means for selecting between placing said second input signal, the complement of said second input signal, and a constant value on said second input terminal.

Claim 45

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and further comprising: means for receiving a first input signal and placing said first input signal on said first input terminal; means for receiving a second input signal; means for selecting between placing said second input signal, the complement of said second input signal, and a constant value on said second input terminal.

Claim 46

A programmable logic device as in claim 32 in which said means for selecting comprises: means for replacing said second input signal with a first constant value; means for controlling said means for replacing; and means for selectively inverting said first constant value.

Claim 47

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and each logic block having at least: a first circuit and a second circuit, said carry-out terminal of said first circuit being connected to said carry-in terminal of said second circuit, said carry-out terminal of said second circuit being coupled to a carry-out terminal of said logic block; at least one carry-in terminal of said logic block; and means for using a signal on one of said at least one carry-in terminal of said logic block as a carry-in signal on said carry-in terminal of said first circuit; in which said second circuit further comprises: means for comparing a signal on said carry-out terminal of said first circuit to said carry-in signal on said first circuit, thereby being useful for detecting an overflow condition.

Claim 48

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and each logic block having at least: a first circuit and a second circuit, said carry-out terminal of said first circuit being connected to said carry-in terminal of said second circuit, said carry-out terminal of said second circuit being coupled to a carry-out terminal of said logic block; at least one carry-in terminal of said logic block; and means for using a signal on one of said at least one carry-in terminal of said logic block as a carry-in signal on said carry-in terminal of said first circuit; in which said second circuit further comprises: means for comparing a signal on said carry-out terminal of said first circuit to said carry-in signal on said first circuit, thereby being useful for detecting an overflow condition.

Claim 49

A programmable logic device as in claim 34 in which said means for comparing comprises: a first multiplexer for selecting between said carry-in signal of said first circuit and a first input signal to said second circuit; a second multiplexer for selecting between said carry-out signal of said first circuit and a second input signal to said second circuit; means for controlling said first and second multiplexers; means for generating the XOR function of signals provided by said first and second multiplexers.

Claim 50

A programmable logic device as in claim 35 in which said means for generating the XOR function of signals provided by said multiplexers comprises a combinatorial function generator.

Claim 51

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and controllable means for selectively propagating said signal on said carry-in terminal to said carry-out terminal; or propagating said signal on one of said first input terminal and said second input terminal to said carry-out terminal.

Claim 52

A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: a first input terminal and a second input terminal; a carry-in terminal and a carry-out terminal; first switching means for connecting said first input terminal to said carry-out terminal; second switching means for connecting said carry-in terminal to said carry-out terminal; control means for causing said first switching means to connect said first input terminal to said carry-out terminal and for causing said second switching means to connect said carry-in terminal to said carry-out terminal; said control means causing said first switching means to connect said first input terminal to said carry-out terminal when and only when the logic value of a signal on said first input terminal is equal to the logic value of a signal on said second input terminal, and said control means causing said second switching means to connect said carry-in terminal to said carry-out terminal when and only when said logic value of said signal on said first input terminal does not equal said logic value of said signal on said second input terminal; said logic block further having means for generating at an output terminal one of a plurality of logic functions of a given set of inputs, at least one of said first and second input terminal further providing input to said means for generating one of a plurality of logic functions; and controllable means for selectively propagating said signal on said carry-in terminal to said carry-out terminal; or propagating said signal on one of said first input terminal and said second input terminal to said carry-out terminal.