US5682107A
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US
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FPGA architecture with repeatable tiles including routing matrices and logic matrices
Assignee: Xilinx Inc
•
Filing: 1996-03-19
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Granted: 1997-10-28
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Expires: 2016-03-19
Abstract
Abstract An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.
Inventors
- 👤 Danesh Tavana
- 👤 Wilson K. Yee
- 👤 Victor A. Holen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:20
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17704; H03K19/1778; H03K19/17796
Claims Analysis
Total Claims: 79
Claim 1
Independent Claim
128 words
An FPGA tile architecture having a plurality of tiles, each said tile comprising: a configurable logic block matrix, including logic circuitry; a programmable routing matrix comprising: routing lines extending to edges of said tile in more than one compass direction; inter-matrix lines extending into said configurable logic block matrix and connectable to said configurable logic block matrix to provide bidirectional signal flow between said programmable routing matrix and said configurable logic block matrix; and a plurality of programmable connectors being arranged to connect one of said inter-matrix lines to a plurality of said routing lines, whereby one of said inter-matrix lines programmably connects routing lines extending to edges of said tile in one compass direction to routing lines extending to edges of said tile in another compass direction.
Claim 2
Dependent Claim
128 words
An FPGA tile architecture having a plurality of tiles, each said tile comprising: a configurable logic block matrix, including logic circuitry; a programmable routing matrix comprising: routing lines extending to edges of said tile in more than one compass direction; inter-matrix lines extending into said configurable logic block matrix and connectable to said configurable logic block matrix to provide bidirectional signal flow between said programmable routing matrix and said configurable logic block matrix; and a plurality of programmable connectors being arranged to connect one of said inter-matrix lines to a plurality of said routing lines, whereby one of said inter-matrix lines programmably connects routing lines extending to edges of said tile in one compass direction to routing lines extending to edges of said tile in another compass direction.
Claim 3
Dependent Claim
15 words
The FPGA tile architecture of claim 1 wherein said tiles are identical in logic content.
Claim 4
Dependent Claim
18 words
The FPGA tile architecture of claim 1 wherein one tile is different in logic content from another tile.
Claim 5
Dependent Claim
23 words
The FPGA tile architecture of claim 1 in which others of said tiles are positioned on all four sides of each said tile.
Claim 6
Dependent Claim
39 words
The FPGA tile architecture of claim 1 further including a plurality of long lines extending horizontally through said tile, wherein at least one of said plurality of long lines is coupled to at least one of said inter-matrix lines.
Claim 7
Dependent Claim
39 words
The FPGA tile architecture of claim 5 further including a plurality of long lines extending vertically through said tile, wherein at least one of said plurality of long lines is coupled to at least one of said inter-matrix lines.
Claim 8
Dependent Claim
25 words
The FPGA tile architecture of claim 6 further including a global horizontal line coupled to said configurable logic block matrix and said programmable routing matrix.
Claim 9
Dependent Claim
25 words
The FPGA tile architecture of claim 7 further including a global vertical line coupled to said configurable logic block matrix and said programmable routing matrix.
Claim 10
Dependent Claim
28 words
The FPGA tile architecture of claim 8 further including a multiple length line, wherein said multiple length line couples programmable routing matrices that are not in adjacent tiles.
Claim 11
Dependent Claim
28 words
The FPGA tile architecture of claim 9 wherein said multiple length line is a double length line which couples programmable routing matrices that are separated by one tile.
Claim 12
Dependent Claim
30 words
The FPGA tile architecture of claim 1 further comprising a carry-out line and a carry-in line, wherein said carry-out line is coupled to a carry-in line in an adjacent tile.
Claim 13
Dependent Claim
21 words
The FPGA tile architecture of claim 11 wherein said carry-in line is coupled to a carry-out line in an adjacent tile.
Claim 14
Dependent Claim
79 words
The FPGA tile architecture of claim 9 further comprising: a plurality of input lines to said configurable logic block matrix; a plurality of output lines from said configurable logic block matrix, wherein at least one of said plurality of input lines is coupled to one of said plurality of output lines in an adjacent tile, and at least one of said plurality of output lines is coupled to one of said plurality of input lines in an adjacent tile.
Claim 15
Dependent Claim
51 words
The FPGA tile architecture of claim 1 wherein said configurable logic block matrix comprises: a plurality of logic block input lines programmably connected to said inter-matrix lines through an input interconnect structure; and a plurality of logic block output lines programmably connected to said inter-matrix lines through an output interconnect structure.
Claim 16
Dependent Claim
36 words
The FPGA tile architecture of claim 14 wherein said configurable logic block matrix further includes a configurable logic block coupled between said plurality of logic block input lines and said plurality of logic block output lines.
Claim 17
Dependent Claim
21 words
The FPGA tile architecture of claim 15 wherein said output interconnect structure is more fully pipulated than said input interconnect structure.
Claim 18
Dependent Claim
15 words
The FPGA tile architecture of claim 16 wherein said input interconnect structure is sparsely pipulated.
Claim 19
Dependent Claim
15 words
The FPGA tile architecture of claim 17 wherein said output interconnect structure is fully pipulated.
Claim 20
Dependent Claim
31 words
The FPGA tile architecture of claim 15 wherein said configurable logic block matrix further includes a feedback interconnect structure for programmably connecting said output lines to said logic block input lines.
Claim 21
Dependent Claim
31 words
The FPGA tile architecture of claim 14 wherein said configurable logic block matrix further includes a general interconnect structure for programmably connecting said inter-matrix lines to said logic block input lines.
Claim 22
Dependent Claim
18 words
The FPGA tile architecture of claim 1 wherein at least one of said inter-matrix lines includes a buffer.
Claim 23
Dependent Claim
31 words
The FPGA tile architecture of claim 15 wherein said configurable logic block includes a plurality of function generators, each function generator coupled to a subset of said logic block input lines.
Claim 24
Dependent Claim
40 words
The FPGA tile architecture of claim 22 wherein said configurable logic block further includes a plurality of multiplexers, wherein at least one of said plurality of function generators provides a signal to at least one of said plurality of multiplexers.
Claim 25
Dependent Claim
40 words
The FPGA tile architecture of claim 23 wherein said configurable logic block further includes a plurality of registers, and wherein at least one of said plurality of multiplexers provides a signal to at least one of said plurality of registers.
Claim 26
Dependent Claim
21 words
The FPGA tile architecture of claim 24 wherein at least one function generator is coupled to one logic block output line.
Claim 27
Dependent Claim
20 words
The FPGA tile architecture of claim 25 wherein at least one multiplexer is coupled to one logic block output line.
Claim 28
Dependent Claim
20 words
The FPGA tile architecture of claim 26 wherein at least one register is coupled to one logic block output line.
Claim 29
Dependent Claim
18 words
The FPGA tile architecture of claim 27 wherein at least one multiplexer is coupled to said carry-out line.
Claim 30
Dependent Claim
18 words
The FPGA tile architecture of claim 28 wherein at least one multiplexer is coupled to said carry-in line.
Claim 31
Dependent Claim
30 words
The FPGA tile architecture of claim 22 wherein said configurable logic block further includes groups of multiplexers, each group of multiplexers coupled to one of said plurality of function generators.
Claim 32
Dependent Claim
36 words
The FPGA tile architecture of claim 30 wherein said configurable logic block further includes a plurality of register means, and wherein each group of multiplexers provides a signal to one of said plurality of register means.
Claim 33
Dependent Claim
19 words
The FPGA tile architecture of claim 31 wherein each function generator is coupled to one logic block output line.
Claim 34
Dependent Claim
25 words
The FPGA tile architecture of claim 32 wherein at least one multiplexer of each group of multiplexers is coupled to one logic block output line.
Claim 35
Dependent Claim
18 words
The FPGA tile architecture of claim 33 wherein each register is coupled to one logic block output line.
Claim 36
Dependent Claim
23 words
The FPGA tile architecture of claim 34 wherein at least one multiplexer is coupled to a carry-out line of said configurable logic block.
Claim 37
Dependent Claim
23 words
The FPGA tile architecture of claim 35 wherein at least one multiplexer is coupled to a carry-in line of said configurable logic block.
Claim 38
Dependent Claim
27 words
The FPGA tile architecture of claim 14 wherein said output interconnect structure includes a first plurality of transistors, each transistor provided on one logic block output line.
Claim 39
Dependent Claim
33 words
The FPGA tile architecture of claim 35 wherein said output interconnect structure includes a first plurality of memory devices, each memory device controlling the state of a subset of said plurality of transistors.
Claim 40
Dependent Claim
36 words
The FPGA tile architecture of claim 1 further comprising a plurality of long lines wherein said programmable connectors further couple those of said plurality of long lines extending horizontally through said tile to said inter-matrix lines.
Claim 41
Dependent Claim
29 words
The FPGA tile architecture of claim 39 wherein said programmable connectors further couple those of said plurality of long lines extending vertically through said tile to said inter-matrix lines.
Claim 42
Dependent Claim
48 words
The FPGA tile architecture of claim 20 wherein said input interconnect structure and said general interconnect structure include a first plurality of transistors, said first plurality of transistors provided on a subset of said plurality of inter-matrix lines and on a subset of said plurality of input lines.
Claim 43
Dependent Claim
33 words
The FPGA tile architecture of claim 41 wherein said input interconnect structure and said general interconnect structure include at least one memory device that controls the state of said first plurality of transistors.
Claim 44
Dependent Claim
27 words
The FPGA tile architecture of claim 1 further comprising a multiple length line wherein said programmable connectors further couple said multiple length line to said inter-matrix lines.
Claim 45
Dependent Claim
21 words
The FPGA tile architecture of claim 43 wherein said programmable connectors further couple a global horizontal line to an inter-matrix line.
Claim 46
Dependent Claim
21 words
The FPGA tile architecture of claim 44 wherein said programmable connectors further couple a global vertical line to an inter-matrix line.
Claim 47
Dependent Claim
45 words
The FPGA tile architecture of claim 6 wherein at least one of said long lines, either extending horizontally or vertically across said tile, includes a long line splitter, wherein said long line splitter includes means for preventing conduction of said at least one long line.
Claim 48
Dependent Claim
16 words
The FPGA tile architecture of claim 46 wherein said means for preventing conduction includes a transistor.
Claim 49
Dependent Claim
14 words
The FPGA tile architecture of claim 47 wherein said transistor is an n-type transistor.
Claim 50
Dependent Claim
32 words
The FPGA tile architecture of claim 20 further including a plurality of edge tiles, wherein each edge tile is coupled to at least one other edge tile and one of said tiles.
Claim 51
Dependent Claim
19 words
The FPGA tile architecture of claim 49 wherein each edge tile is further coupled to an input/output (I/O) device.
Claim 52
Dependent Claim
24 words
The FPGA tile architecture of claim 50 wherein said I/O device is coupled to a pad which provides an external connection to said chip.
Claim 53
Dependent Claim
16 words
The FPGA tile architecture of claim 51 wherein an electrostatic discharge device connects to said pad.
Claim 54
Dependent Claim
29 words
The FPGA tile architecture of claim 51 wherein said edge tile includes means for coupling said I/O device to said routing lines, said input lines, and said output lines.
Claim 55
Dependent Claim
26 words
The FPGA tile architecture of claim 53 wherein said means for coupling couples either global horizontal line or a global vertical line to said I/O device.
Claim 56
Dependent Claim
25 words
The FPGA tile architecture of claim 49 further including a plurality of corner tiles, wherein each corner tile is connected to two adjacent edge tiles.
Claim 57
Dependent Claim
33 words
The FPGA tile architecture of claim 55 wherein said corner tile connects a plurality of long lines extending horizontally across said tile to said plurality of long lines extending vertically across said tile.
Claim 58
Dependent Claim
43 words
The FPGA tile architecture of claim 55 wherein said corner tile includes a corner tile interconnect structure for programmably connecting a plurality of long lines extending horizontally across said tile and a subset of said plurality of routing lines to a selected circuit.
Claim 59
Dependent Claim
16 words
The FPGA tile architecture of claim 57 wherein said selected circuit is a boundary scan block.
Claim 60
Dependent Claim
15 words
The FPGA tile architecture of claim 57 wherein said selected circuit is an oscillator/counter circuit.
Claim 61
Dependent Claim
15 words
The FPGA tile architecture of claim 57 wherein said selected circuit is a start-up block.
Claim 62
Dependent Claim
15 words
The FPGA tile architecture of claim 57 wherein said selected circuit is a read-back unit.
Claim 63
Dependent Claim
34 words
The FPGA tile architecture of claim 55 wherein said edge tiles further include means for programmably connecting an external pin to at least one of said long lines extending horizontally across said core tile.
Claim 64
Dependent Claim
161 words
An FPGA tile architecture comprising: a plurality of paired structures, each paired structure including: a configurable logic block matrix, including logic circuitry; a programmable routing matrix; a plurality of lines for connecting said configurable logic block matrix to said programmable routing matrix, wherein each of said plurality of lines provides for flow of signals from said configurable logic block matrix to said programmable routing matrix and for flow of signals from said programmable routing matrix to said configurable logic block matrix, and connects one of said lines in said programmable routing matrix to another of the lines in the programmable routing matrix; and means for connecting said programmable routing matrix to other programmable routing matrices in other paired structures, wherein said means for connecting comprises: a plurality of single length lines which connect a first programmable routing matrix to adjacent programmable routing matrices; a plurality of double length lines which connect said first programmable routing matrix to nonadjacent programmable routing matrices.
Claim 65
Dependent Claim
161 words
An FPGA tile architecture comprising: a plurality of paired structures, each paired structure including: a configurable logic block matrix, including logic circuitry; a programmable routing matrix; a plurality of lines for connecting said configurable logic block matrix to said programmable routing matrix, wherein each of said plurality of lines provides for flow of signals from said configurable logic block matrix to said programmable routing matrix and for flow of signals from said programmable routing matrix to said configurable logic block matrix, and connects one of said lines in said programmable routing matrix to another of the lines in the programmable routing matrix; and means for connecting said programmable routing matrix to other programmable routing matrices in other paired structures, wherein said means for connecting comprises: a plurality of single length lines which connect a first programmable routing matrix to adjacent programmable routing matrices; a plurality of double length lines which connect said first programmable routing matrix to nonadjacent programmable routing matrices.
Claim 66
Dependent Claim
39 words
The FPGA tile architecture of claim 63 further comprising means for connecting said configurable logic block matrix in one paired structure to a plurality of configurable logic block matrices in other paired structures without using said programmable routing matrix.
Claim 67
Dependent Claim
28 words
The FPGA tile architecture of claim 63 further comprising: a plurality of long lines, each long line being programmably connectable to a plurality of adjacent programmable routing matrices.
Claim 68
Dependent Claim
110 words
An FPGA tile architecture having a plurality of tiles, each said tile comprising: a configurable logic block matrix, including logic circuitry; a programmable routing matrix; inter-matrix lines and lines directly connecting said configurable logic block matrix to said programmable routing matrix so as to provide for signal flow from said configurable logic block matrix to said programmable routing matrix and to provide for signal flow from said programmable routing matrix to said configurable logic block matrix; and routing lines directly connecting said programmable routing matrix to programmable routing matrices in other said tiles, each said routing line being programmably connectable in said programmable routing matrix to another said routing line.
Claim 69
Dependent Claim
110 words
An FPGA tile architecture having a plurality of tiles, each said tile comprising: a configurable logic block matrix, including logic circuitry; a programmable routing matrix; inter-matrix lines and lines directly connecting said configurable logic block matrix to said programmable routing matrix so as to provide for signal flow from said configurable logic block matrix to said programmable routing matrix and to provide for signal flow from said programmable routing matrix to said configurable logic block matrix; and routing lines directly connecting said programmable routing matrix to programmable routing matrices in other said tiles, each said routing line being programmably connectable in said programmable routing matrix to another said routing line.
Claim 70
Dependent Claim
96 words
The tile based FPGA architecture of claim 66 wherein some of said tiles comprise core tiles in the interior of said FPGA and some of said tiles comprise edge tiles near the edge of said FPGA, and further including a plurality of horizontal long lines extending through each row of said core tiles and vertical long lines extending through each column of said core tiles wherein each edge tile includes a general interconnect structure, wherein said plurality of horizontal long lines and said plurality of vertical long lines are programmably connected to said general interconnect structure.
Claim 71
Dependent Claim
32 words
The tile based FPGA architecture of claim 67 further including at least one pad, wherein said at least one pad is programmably connected to the general interconnect structure of an edge tile.
Claim 72
Dependent Claim
29 words
The tile based FPGA architecture of claim 68 further including a plurality of pads, wherein each pad is programmably connected to the general interconnect structure of an edge tile.
Claim 73
Dependent Claim
27 words
The tile based FPGA architecture of claim 68 wherein said at least one pad is programmably connected to the general interconnect structure via a pad interconnect structure.
Claim 74
Dependent Claim
24 words
The tile based FPGA architecture of claim 70 wherein both said general interconnect structure and said pad interconnect structure include programmable interconnection points (PIPs).
Claim 75
Dependent Claim
22 words
The tile based FPGA architecture of claim 71 wherein said pad interconnect structure provides more PIPs than does said general interconnect structure.
Claim 76
Dependent Claim
17 words
The tile based FPGA architecture of claim 72 wherein said pad interconnect structure is substantially fully pipulated.
Claim 77
Dependent Claim
16 words
The tile based FPGA architecture of claim 73 wherein said general interconnect structure is sparsely pipulated.
Claim 78
Dependent Claim
158 words
An FPGA tile architecture comprising a plurality of paired structures, each paired structure including: a configurable logic block matrix, including logic circuitry; a programmable routing matrix; a plurality of lines connecting said configurable logic block matrix to said programmable routing matrix, wherein each of said plurality of lines provides for flow of signals from said configurable logic block matrix to said programmable routing matrix and for flow of signals from said programmable routing matrix to said configurable logic block matrix, and connects one of said lines in said programmable routing matrix to another of the lines in the programmable routing matrix; and lines connecting said programmable routing matrix to other programmable routing matrices in other paired structures, wherein said lines comprise: a plurality of single length lines which connect a first programmable routing matrix to adjacent programmable routing matrices; and a plurality of double length lines which connect said first programmable routing matrix to nonadjacent programmable routing matrices.
Claim 79
Dependent Claim
158 words
An FPGA tile architecture comprising a plurality of paired structures, each paired structure including: a configurable logic block matrix, including logic circuitry; a programmable routing matrix; a plurality of lines connecting said configurable logic block matrix to said programmable routing matrix, wherein each of said plurality of lines provides for flow of signals from said configurable logic block matrix to said programmable routing matrix and for flow of signals from said programmable routing matrix to said configurable logic block matrix, and connects one of said lines in said programmable routing matrix to another of the lines in the programmable routing matrix; and lines connecting said programmable routing matrix to other programmable routing matrices in other paired structures, wherein said lines comprise: a plurality of single length lines which connect a first programmable routing matrix to adjacent programmable routing matrices; and a plurality of double length lines which connect said first programmable routing matrix to nonadjacent programmable routing matrices.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-27 | 2001-04-28 | 2001-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-27 | 2005-04-28 | 2005-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-27 | 2009-04-28 | 2009-10-28 | $7700.00 | Window Closed / Lapsed |