EP0748049A2
Expired / Lapsed
EP
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Interconnection architecture for coarse-grained programmable logic device
Assignee: Altera Corp
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Filing: 1996-05-31
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Granted: —
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Expires: 2016-05-31
Abstract
Abstract A new programmable logic device architecture with an improved LAB and improved interconnection resources. For interconnecting signals to and from the LABs (200), the global interconnection resources include switch boxes (310), long lines (340 and 350), double lines (360 and 370), single lines (385), and half- (330) and partially populated (320) multiplexer regions. The LAB includes two levels of function blocks. In a first level, there are eight four-input function blocks (601). In a second level, there are two four-input function blocks (670) and four secondary two-input function blocks (672). In one embodiment, these function blocks are implemented using look-up tables (LUTs). The LAB has combinatorial and registered outputs. The LAB also contains storage blocks (691) for implementing sequential or registered logic functions. The LAB has a carry chain for implementing logic functions requiring carry bits. The LAB may also be configured to implement a random access memory.
Inventors
- 👤 Richard G. Cliff
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 07:54
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/1733; H03K19/1737; H03K19/17704; H03K19/17724; H03K19/17728; H03K19/17736; H03K19/1776; H03K19/1778
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
90 words
A logic array block for a programmable logic device comprising: a first dedicated input; a first four-input function block for implementing logic functions; a second four-input function block for implementing logic functions; a two-input function block for implementing logic functions, wherein an output of said first four-input function block is coupled to a first input of said two-input function block; and a first multiplexer block, selectively coupling said first dedicated input and said output of said first four-input function block to a first input of said second four-input function block.
Claim 2
Dependent Claim
58 words
The logic array block of claim 1 further comprising a local interconnect region, programmably coupling said output of said first four-input function block, an output of said second four-input function block, and an output of said two-input function block to inputs of said logic array block, without passing through a global interconnect region of said programmable logic device.
Claim 3
Dependent Claim
34 words
The logic array block of claim 1 further comprising a third four-input function block, wherein an output of said third four-input function block is coupled to a second input of said two-input function block.
Claim 4
Dependent Claim
42 words
The logic array block of claim 3 further comprising: a second dedicated input; a second multiplexer block, selectively coupling said second dedicated input and said output of said third four-input function block to a second input of said second four-input function block.
Claim 5
Dependent Claim
42 words
The logic array block of claim 1 further comprising: a storage block for storing data; and a second multiplexer block, selectively coupling said output of said first four-input function block and said first dedicated input to an input of said storage block.
Claim 6
Dependent Claim
49 words
The logic array block of claim 1 further comprising: a storage block for storing data; and a second multiplexer block, selectively coupling said output of said first four-input function block, said output of said two-input function block, and said first dedicated input to an input of said storage block.
Claim 7
Dependent Claim
50 words
The logic array block of claim 4 further comprising: a storage block for storing data; and a second multiplexer block, selectively coupling said output of said second four-input function block, said output of said third four-input function block, and said second dedicated input to an input of said storage block.
Claim 8
Dependent Claim
65 words
The logic array block of claim 1 further comprising: a combinatorial output, programmably coupling said first function block to inputs to said logic array block via a local interconnect structure, without using a global interconnect structure; and a register, programmably coupled to said first function block and said first dedicated input, said register providing a registered output, not programmably coupled to said local interconnect structure.
Claim 9
Dependent Claim
17 words
A system incorporating a programmable logic device with a logic array block as recited in claim 1.
Claim 10
Dependent Claim
92 words
A logic array block for a programmable logic device comprising: a first dedicated input; a first programmable function block for implementing logic functions; a second programmable function block, programmably coupled to said dedicated input and said first programmable function block, said second programmable function block for implementing logic functions; and a local interconnect region, programmably coupling an output of said first programmable function block and an output of said second programmable function block to inputs of said logic array block, without passing through a global interconnect region of said programmable logic device.
Claim 11
Dependent Claim
67 words
The logic array block of claim 10 further comprising a third programmable function block, coupled to said first programmable function block, said third programmable function block for implementing logic functions, wherein an output of said third programmable function block is programmably coupled through said local interconnect structure to said inputs of said logic array block, without passing through said global interconnect region of said programmable logic device.
Claim 12
Dependent Claim
76 words
The logic array block of claim 11 further comprising: a second dedicated input; a fourth programmable function block, coupled to said third programmable function block, and programmably coupled to said second dedicated input and said second programmable function block, wherein an output of said fourth programmable function block is programmably coupled through said local interconnect structure to said inputs of said logic array block, without passing through said global interconnect region of said programmable logic device.
Claim 13
Dependent Claim
25 words
The logic array block of claim 10 further comprising: a storage block, programmably coupled to said first dedicated input and said first programmable function block.
Claim 14
Dependent Claim
30 words
The logic array block of claim 11 further comprising: a storage block, programmably coupled to said first dedicated input, said first programmable function block, and said third programmable function block.
Claim 15
Dependent Claim
23 words
The logic array block of claim 13 wherein an output of said storage block is not programmably coupled to said local interconnect structure.
Claim 16
Dependent Claim
22 words
The logic array block of claim 10 wherein said first programmable function block and said second programmable function block are substantially identical.
Claim 17
Dependent Claim
34 words
The logic array block of claim 11 wherein said first programmable function block and said second programmable function block are four-input look-up tables and said third programmable function block is a two-input look-up table.
Claim 18
Dependent Claim
20 words
The logic array block of claim 11 wherein said programmable function blocks are implemented in a static random access memory.
References Cited (Backward Citations)
No citation records indexed.
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