US5481206A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for fast carry and logic
Assignee: Xilinx Inc
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Filing: 1994-09-20
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Granted: 1996-01-02
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Expires: 2014-09-20
Abstract
Abstract Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The circuit includes additional structures to allow the fast carry hardware to perform additional commonly used functions.
Inventors
- 👤 Bernard J. New
- 👤 Kerry M. Pierce
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:19
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/506; G06F7/507; G06F7/501; G06F7/503; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1737; G06F2207/00; G06F2207/38; G06F2207/48; G06F2207/4802; G06F2207/4812
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
116 words
A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: an input terminal for providing a first input signal (A i ); a ripple-in terminal (C i ) and a ripple-out terminal (C i+1 ); a ripple-chain multiplexer (923) for connecting one of said input terminal and said ripple-in terminal to said ripple-out terminal; a lookup table (903) for generating a function of said first input signal and at least one other input signal; and a control multiplexer (804) for controlling said ripple-chain multiplexer, said control multiplexer being controlled to select from at least two input signals, one of said signals being provided by said lookup table.
Claim 2
Dependent Claim
116 words
A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: an input terminal for providing a first input signal (A i ); a ripple-in terminal (C i ) and a ripple-out terminal (C i+1 ); a ripple-chain multiplexer (923) for connecting one of said input terminal and said ripple-in terminal to said ripple-out terminal; a lookup table (903) for generating a function of said first input signal and at least one other input signal; and a control multiplexer (804) for controlling said ripple-chain multiplexer, said control multiplexer being controlled to select from at least two input signals, one of said signals being provided by said lookup table.
Claim 3
Dependent Claim
106 words
A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: an input terminal for providing a first input signal (A i ); an input select multiplexer (801) for providing one of said first input signal and another signal (802) as an output of said input select multiplexer; a ripple-in terminal (C i ) and a ripple-out terminal (C i+1 ); a ripple-chain multiplexer (923) for connecting one of said output of said input select multiplexer and said ripple-in terminal to said ripple-out terminal; a lookup table (903) for generating a signal which can control said ripple-chain multiplexer.
Claim 4
Dependent Claim
106 words
A programmable logic device comprising an array of logic blocks, each logic block having at least one circuit comprising: an input terminal for providing a first input signal (A i ); an input select multiplexer (801) for providing one of said first input signal and another signal (802) as an output of said input select multiplexer; a ripple-in terminal (C i ) and a ripple-out terminal (C i+1 ); a ripple-chain multiplexer (923) for connecting one of said output of said input select multiplexer and said ripple-in terminal to said ripple-out terminal; a lookup table (903) for generating a signal which can control said ripple-chain multiplexer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-01 | 1999-07-03 | 2000-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-01 | 2003-07-03 | 2004-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-01 | 2007-07-03 | 2008-01-02 | $7700.00 | Window Closed / Lapsed |