US5352940A
Expired / Lapsed
US
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Ram convertible look-up table based macrocell for PLDs
Assignee: Altera Corp
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Filing: 1993-05-27
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Granted: 1994-10-04
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Expires: 2013-05-27
Abstract
Abstract A macrocell for use in programmable logic devices (PLDs) that provides for standard memory functions with minimum overhead circuitry. In a PLD that uses static random access memory (SRAM) as its configuration host, the circuit of the present invention enables the SRAM to be programmed via bidirectional look-up tables. In a user mode, macrocell bidirectional look-up table implements the configured logic, while in supervisor and memory modes the look-up table acts as an address decoder for the SRAM. A tristate buffer and two pass gates to direct data out of, and drive data into, the SRAM cells through the look-up table are the only additional circuitry required.
Inventors
- 👤 James Watson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 03:51
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1737
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
92 words
A macrocell for use in reconfigurable logic array systems, comprising: memory means for storing programming information; a bidirectional look-up table coupled to the memory means and having an input/output terminal, and a plurality of select inputs; and means, coupled to the look-up table, for transferring the programming information via the input/output terminal of the look-up table to a selected address in the memory means in a first mode of operation, and transferring stored programming information from an address in the memory means to the input/output terminal in a second mode of operation.
Claim 2
Dependent Claim
92 words
A macrocell for use in reconfigurable logic array systems, comprising: memory means for storing programming information; a bidirectional look-up table coupled to the memory means and having an input/output terminal, and a plurality of select inputs; and means, coupled to the look-up table, for transferring the programming information via the input/output terminal of the look-up table to a selected address in the memory means in a first mode of operation, and transferring stored programming information from an address in the memory means to the input/output terminal in a second mode of operation.
Claim 3
Dependent Claim
26 words
A macrocell as recited in claim 1 wherein the bidirectional look-up table includes four select inputs to connect one of sixteen terminals to the input/output terminal.
Claim 4
Dependent Claim
45 words
A macrocell as recited in claim 2 wherein the memory means comprises sixteen rows of a plurality of serially coupled static random access memory cells, with each one of the sixteen rows being coupled to one of the sixteen terminals of the bidirectional look-up table.
Claim 5
Dependent Claim
89 words
A macrocell as recited in claim 1 wherein the transferring means comprises: a selection logic having a first input coupled to the look-up table input/output terminal, a second input coupled to receive the programming information, a mode select input, and an output; register means, having an input coupled to the selection logic output, for registering said selection logic output; and means, coupled to an output of the register means and controlled by the mode select input, for feeding back the register means output to the look-up table input/output terminal.
Claim 6
Dependent Claim
56 words
A macrocell as recited in claim 4 wherein the feeding back means comprises: driver means, coupled at the output of the register means, for driving the programming information into the look-up table; and a pass gate coupling an output of the driver means to the look-up table input/output terminal, and controlled by the mode select input.
Claim 7
Dependent Claim
13 words
A macrocell as recited in claim 5 wherein the driver means is tristatable.
Claim 8
Dependent Claim
15 words
A macrocell as recited in claim 4 wherein the register means is a clocked flip-flop.
Claim 9
Dependent Claim
70 words
A macrocell as recited in claim 4 further comprising: a buffer circuit having an input and an output, for coupling the look-up table input/output terminal at its input to the selection logic input at its output; and a second selection logic having a first input coupled to the register means output, a second input coupled to the buffer circuit output, and an output coupled to an output of the macrocell.
Claim 10
Dependent Claim
29 words
A macrocell as recited in claim 8 further comprising a pass gate coupling the macrocell output to the look-up table input/output terminal, and controlled by the mode selection input.
Claim 11
Dependent Claim
23 words
A macrocell as recited in claim 9 wherein the second selection logic further includes a tristate input coupled to the mode selection input.
Claim 12
Dependent Claim
113 words
A macrocell for use in reconfigurable logic array systems, comprising: memory means for storing programming information; a bidirectional look-up table coupled to the memory means and having an input/output terminal, and a plurality of select inputs; a selection logic having a first input coupled to the look-up table input/output terminal, a second input coupled to receive the programming information, a mode select input, and an output; register means, having an input coupled to the selection logic output, for registering said selection logic output; and means, coupled to an output of the register means and controlled by the mode select input, for feeding back the register means output to the look-up table input/output terminal.
Claim 13
Dependent Claim
113 words
A macrocell for use in reconfigurable logic array systems, comprising: memory means for storing programming information; a bidirectional look-up table coupled to the memory means and having an input/output terminal, and a plurality of select inputs; a selection logic having a first input coupled to the look-up table input/output terminal, a second input coupled to receive the programming information, a mode select input, and an output; register means, having an input coupled to the selection logic output, for registering said selection logic output; and means, coupled to an output of the register means and controlled by the mode select input, for feeding back the register means output to the look-up table input/output terminal.
Claim 14
Dependent Claim
81 words
A macrocell as recited in claim 11, further comprising: a second selection logic having a first input coupled to the register means output, a second input coupled to the look-up terminal input/output terminal, and an output coupled to an output of the macrocell; a buffer inserted between the look-up table input/output terminal and the first input of the selection logic; and a pass gate coupling the macrocell output to the look-up table input/output terminal, and controlled by the mode select input.
Claim 15
Dependent Claim
86 words
In reconfigurable array logic systems having a plurality of macrocells, with each macrocell including a look-up table coupled to a memory structure, a method for converting the macrocell to a memory unit, comprising the steps of: coupling an output of the macrocell to an input/output terminal of a bidirectional look-up table via a pass gate; selecting a memory write mode of operation by enabling the pass gate; and writing into the memory structure through the macrocell output, using the bidirectional look-up table as an address decoder.
Claim 16
Dependent Claim
86 words
In reconfigurable array logic systems having a plurality of macrocells, with each macrocell including a look-up table coupled to a memory structure, a method for converting the macrocell to a memory unit, comprising the steps of: coupling an output of the macrocell to an input/output terminal of a bidirectional look-up table via a pass gate; selecting a memory write mode of operation by enabling the pass gate; and writing into the memory structure through the macrocell output, using the bidirectional look-up table as an address decoder.
Claim 17
Dependent Claim
48 words
A method for converting a macrocell into a memory unit as recited in claim 13, further comprising the steps of: selecting a memory read mode of operation by disabling the pass gate; and reading data from the memory structure using the bidirectional look-up table as an address decoder.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-03 | 1998-04-04 | 1998-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-03 | 2002-04-04 | 2002-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-03 | 2006-04-04 | 2006-10-04 | $7700.00 | Window Closed / Lapsed |