Method of manufacturing a semiconductor IC device having single transistor type nonvolatile memory cells

Claim 1

A method of manufacturing a semiconductor memory device including a memory cell constituted by a MISFET, comprising the steps of: (a) providing a semiconductor substrate having a main surface, with a first gate insulating film of said MISFET formed on said main surface, a floating gate electrode of said MISFET formed on said first gate insulating film, a second gate insulating film of said MISFET formed on said floating gate electrode, and a control gate electrode of said MISFET formed on said second gate insulating film; (b) forming a first semiconductor region in said semiconductor substrate by introducing an impurity in said semiconductor substrate; and (c) forming a second semiconductor region in said semiconductor substrate by introducing an impurity in said semiconductor substrate; wherein a channel forming region of said MISFET is formed in said semiconductor substrate between said first semiconductor region and said second semiconductor region, wherein said first and said second semiconductor regions are extended beneath said floating gate electrode, respectively, wherein said impurity introduced in said step (c) is the same impurity as said impurity introduced in said step (b), wherein an impurity concentration of said first semiconductor region is greater than that of said second semiconductor region, and wherein carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.

Claim 2

A method of manufacturing a semiconductor memory device including a memory cell constituted by a MISFET, comprising the steps of: (a) providing a semiconductor substrate having a main surface, with a first gate insulating film of said MISFET formed on said main surface, a floating gate electrode of said MISFET formed on said first gate insulating film, a second gate insulating film of said MISFET formed on said floating gate electrode, and a control gate electrode of said MISFET formed on said second gate insulating film; (b) forming a first semiconductor region in said semiconductor substrate by introducing an impurity in said semiconductor substrate; and (c) forming a second semiconductor region in said semiconductor substrate by introducing an impurity in said semiconductor substrate; wherein a channel forming region of said MISFET is formed in said semiconductor substrate between said first semiconductor region and said second semiconductor region, wherein said first and said second semiconductor regions are extended beneath said floating gate electrode, respectively, wherein said impurity introduced in said step (c) is the same impurity as said impurity introduced in said step (b), wherein an impurity concentration of said first semiconductor region is greater than that of said second semiconductor region, and wherein carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.

Claim 7

A method of manufacturing a semiconductor memory device including a memory cell constituted by a first MISFET, and a second MISFET for a peripheral circuit, comprising the steps of: (a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, and a control gate electrode of said first MISFET formed on said second gate insulating film, and with a third gate insulating film of said second MISFET formed on said peripheral circuit forming region, a gate electrode of said second MISFET formed on said third gate insulating film; (b) forming a first semiconductor region in said semiconductor substrate by introducing an impurity into said memory cell forming region; (c) forming a second semiconductor region in said semiconductor substrate by introducing an impurity into said memory cell forming region, wherein said impurity introduced in said step (c) is the same impurity as said impurity introduced in said step (b), wherein an impurity concentration of said first semiconductor region is greater than that of said second semiconductor region, wherein said first and said second semiconductor regions are extended beneath said floating gate electrode, respectiely, and wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said second semiconductor region; (d) forming a third semiconductor region in said semiconductor substrate by introducing an impurity into said peripheral circuit forming region, wherein a dose introduced in said step (d) is lower than the dose introduced in said step (b); (e) after said steps (b), (c), and (d), forming first side wall spacers on both of opposing, end side surfaces of said control and floating gate electrodes in self-alignment with said control and floating gate electrodes, and forming second side wall spacers on both of opposing, end side surfaces of the gate electrode of said second MISFET; and (f) forming a fourth semiconductor region in said semiconductor substrate by introducing an impurity into said peripheral circuit forming region in self-alignment with said second side wall spacers, wherein a dose introduced in said step (f) is greater than the dose introduced in said step (d); wherein said first, second, third and fourth semiconductor regions have a same conductivity type, wherein said third and fourth semiconductor regions serve as a drain region of said second MISFET, and wherein carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.

Claim 8

A method of manufacturing a semiconductor memory device including a memory cell constituted by a first MISFET, and a second MISFET for a peripheral circuit, comprising the steps of: (a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, and a control gate electrode of said first MISFET formed on said second gate insulating film, and with a third gate insulating film of said second MISFET formed on said peripheral circuit forming region, a gate electrode of said second MISFET formed on said third gate insulating film; (b) forming a first semiconductor region in said semiconductor substrate by introducing an impurity into said memory cell forming region; (c) forming a second semiconductor region in said semiconductor substrate by introducing an impurity into said memory cell forming region, wherein said impurity introduced in said step (c) is the same impurity as said impurity introduced in said step (b), wherein an impurity concentration of said first semiconductor region is greater than that of said second semiconductor region, wherein said first and said second semiconductor regions are extended beneath said floating gate electrode, respectiely, and wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said second semiconductor region; (d) forming a third semiconductor region in said semiconductor substrate by introducing an impurity into said peripheral circuit forming region, wherein a dose introduced in said step (d) is lower than the dose introduced in said step (b); (e) after said steps (b), (c), and (d), forming first side wall spacers on both of opposing, end side surfaces of said control and floating gate electrodes in self-alignment with said control and floating gate electrodes, and forming second side wall spacers on both of opposing, end side surfaces of the gate electrode of said second MISFET; and (f) forming a fourth semiconductor region in said semiconductor substrate by introducing an impurity into said peripheral circuit forming region in self-alignment with said second side wall spacers, wherein a dose introduced in said step (f) is greater than the dose introduced in said step (d); wherein said first, second, third and fourth semiconductor regions have a same conductivity type, wherein said third and fourth semiconductor regions serve as a drain region of said second MISFET, and wherein carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.

Claim 13

A method of manufacturing a semiconductor memory device including a memory cell constituted by a first MISFET, and a second MISFET for a peripheral circuit, comprising steps of: (a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, and a control gate electrode of said first MISFET formed on said second gate insulating film, and with a third gate insulating film of said second MISFET formed on said peripheral circuit forming region, a gate electrode of said second MISFET formed on said third gate insulating film; (b) forming a first semiconductor region in said semiconductor substrate by introducing an impurity into said memory cell forming region; (c) forming a second semiconductor region in said semiconductor substrate by introducing an impurity into said memory cell forming region, wherein said impurity introduced in said step (c) is the same impurity as said impurity introduced in said step (b), and wherein an impurity concentration of said first semiconductor region is greater than that of said second semiconductor region; (d) after said steps (b) and (c), depositing a first insulating film over said control gate electrode and said first gate electrode so as to cover said memory cell forming region and said peripheral circuit forming region; and (e) etching said first insulating film to form first side wall spacers on both of opposing, end side surfaces of said control and floating gate electrodes in self-alignment with said control and floating gate electrodes and to form second side wall spacers on both of opposing, end side surfaces of the gate electrode of said second MISFET; wherein said first and said second semiconductor regions are extended beneath said floating gate electrode, respectively, wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said second semiconductor region, and wherein carriers are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.

Claim 14

A method of manufacturing a semiconductor memory device including a memory cell constituted by a first MISFET, and a second MISFET for a peripheral circuit, comprising steps of: (a) providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, and a control gate electrode of said first MISFET formed on said second gate insulating film, and with a third gate insulating film of said second MISFET formed on said peripheral circuit forming region, a gate electrode of said second MISFET formed on said third gate insulating film; (b) forming a first semiconductor region in said semiconductor substrate by introducing an impurity into said memory cell forming region; (c) forming a second semiconductor region in said semiconductor substrate by introducing an impurity into said memory cell forming region, wherein said impurity introduced in said step (c) is the same impurity as said impurity introduced in said step (b), and wherein an impurity concentration of said first semiconductor region is greater than that of said second semiconductor region; (d) after said steps (b) and (c), depositing a first insulating film over said control gate electrode and said first gate electrode so as to cover said memory cell forming region and said peripheral circuit forming region; and (e) etching said first insulating film to form first side wall spacers on both of opposing, end side surfaces of said control and floating gate electrodes in self-alignment with said control and floating gate electrodes and to form second side wall spacers on both of opposing, end side surfaces of the gate electrode of said second MISFET; wherein said first and said second semiconductor regions are extended beneath said floating gate electrode, respectively, wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said second semiconductor region, and wherein carriers are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.

Claim 23

A method of manufacturing a semiconductor memory device including a memory cell constituted by a first MISFET, and a second MISFET for a peripheral circuit, comprising the steps of: providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, and a control gate electrode of said first MISFET formed on said second gate insulating film, and with a third gate insulating film of said second MISFET formed on said peripheral circuit forming region, a first gate electrode of said second MISFET formed on said third gate insulating film; forming a first semiconductor regional said semiconductor substrate by introducing an impurity into said memory cell forming region; forming a second semiconductor region in said semiconductor substrate by introducing an impurity into said memory cell forming region; forming a third semiconductor region in said semiconductor substrate by introducing an impurity into said peripheral circuit forming region; depositing a first insulating film over said control gate electrode and said first gate electrode so as to cover said memory cell forming region and said peripheral circuit forming region; and etching said first insulating film to form first side wall spacers on both of opposing, end side surfaces of said control and floating gate electrodes in self-alignment with said control and floating gate electrodes and to form second side wall spacers on both of opposing, end side surfaces of said first gate electrode, wherein a dose introduced in said second semiconductor region forming step is lower than the dose introduced in said first semiconductor region forming step, wherein said first and second semiconductor regions are extended beneath said floating gate electrode and have the same conductivity type, respectively, wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said second semiconductor region, wherein carriers are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film, and wherein said third semiconductor region serves as a drain region of said second MISFET.

Claim 24

A method of manufacturing a semiconductor memory device including a memory cell constituted by a first MISFET, and a second MISFET for a peripheral circuit, comprising the steps of: providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, and a control gate electrode of said first MISFET formed on said second gate insulating film, and with a third gate insulating film of said second MISFET formed on said peripheral circuit forming region, a first gate electrode of said second MISFET formed on said third gate insulating film; forming a first semiconductor regional said semiconductor substrate by introducing an impurity into said memory cell forming region; forming a second semiconductor region in said semiconductor substrate by introducing an impurity into said memory cell forming region; forming a third semiconductor region in said semiconductor substrate by introducing an impurity into said peripheral circuit forming region; depositing a first insulating film over said control gate electrode and said first gate electrode so as to cover said memory cell forming region and said peripheral circuit forming region; and etching said first insulating film to form first side wall spacers on both of opposing, end side surfaces of said control and floating gate electrodes in self-alignment with said control and floating gate electrodes and to form second side wall spacers on both of opposing, end side surfaces of said first gate electrode, wherein a dose introduced in said second semiconductor region forming step is lower than the dose introduced in said first semiconductor region forming step, wherein said first and second semiconductor regions are extended beneath said floating gate electrode and have the same conductivity type, respectively, wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said second semiconductor region, wherein carriers are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film, and wherein said third semiconductor region serves as a drain region of said second MISFET.

Claim 34

A method of manufacturing a semiconductor memory device including a memory cell constituted by a MISFET, comprising the steps of: providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film of said MISFET formed on said memory cell forming region, a floating gate electrode of said MISFET formed on said first gate insulating film, a second gate insulating film of said MISFET formed on said floating gate electrode, and a control gate electrode of said MISFET formed on said second gate insulating film; forming a first semiconductor region in said semiconductor substrate by introducing an impurity into said semiconductor substrate; and forming a second semiconductor region in said semiconductor substrate by introducing an impurity into said semiconductor substrate, wherein said first and second semiconductor regions have the same conductivity type and are, respectively, extended beneath said floating gate electrode such that an impurity concentration of said second semiconductor region is lower than that of said first semiconductor region, wherein a channel forming region of said MISFET is formed between said first semiconductor region and said second semiconductor region, and wherein carriers are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.

Claim 35

A method of manufacturing a semiconductor memory device including a memory cell constituted by a MISFET, comprising the steps of: providing a semiconductor substrate having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film of said MISFET formed on said memory cell forming region, a floating gate electrode of said MISFET formed on said first gate insulating film, a second gate insulating film of said MISFET formed on said floating gate electrode, and a control gate electrode of said MISFET formed on said second gate insulating film; forming a first semiconductor region in said semiconductor substrate by introducing an impurity into said semiconductor substrate; and forming a second semiconductor region in said semiconductor substrate by introducing an impurity into said semiconductor substrate, wherein said first and second semiconductor regions have the same conductivity type and are, respectively, extended beneath said floating gate electrode such that an impurity concentration of said second semiconductor region is lower than that of said first semiconductor region, wherein a channel forming region of said MISFET is formed between said first semiconductor region and said second semiconductor region, and wherein carriers are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.