EP0286121A2
Expired / Lapsed
EP
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Nonvolatile semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1988-04-08
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Granted: —
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Expires: 2008-04-08
Abstract
Abstract A memory cell of a nonvolatile semiconductor memory device comprises a P conductive type semiconductor substrate (10), first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode (14) formed on the channel region, and a control gate electrode (15) formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.
Inventors
- 👤 Osamu C/O Patent Division Matsumoto
- 👤 Tadashi C/O Patent Division Maruyama
- 👤 Hiroyoshi C/O Patent Division Murata
- 👤 Isao Abe
- 👤 Tomohisa C/O Patent Division Shigematsu
- 👤 Kazuyoshi C/O Patent Division Shinada
- 👤 Yasoji C/O Patent Division Suzuki
- 👤 Ichiro C/O Patent Division Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 13:24
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; G11C16/0425; G11C16/06; G11C16/10; G11C16/12; G11C16/26; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
163 words
A nonvolatile semiconductor memory device comprising: a memory cell (20) including a first conductivity type semiconductor substrate (10), first and second diffusion layers (11, 12) of a second conductivity type formed in said substrate, a channel region (13) formed in the surface region of said substrate and located between said first and second diffusion layers, a floating gate electrode (14) formed on said channel region, a control gate electrode (15) formed on said floating gate electrode, and means (16) for lessening an electric field concentration which occurs between said first layer and said channel region; a control gate line (CG) for supplying predetermined voltages to said control gate electrode, in a read mode and in a write mode; a read line (RL) for supplying predetermined voltages to said first diffusion layer, in the read mode and in the write mode; and a write line (WL) for supplying predetermined voltages to said second diffusion layer, in the read mode and in the write mode.
Claim 2
Dependent Claim
163 words
A nonvolatile semiconductor memory device comprising: a memory cell (20) including a first conductivity type semiconductor substrate (10), first and second diffusion layers (11, 12) of a second conductivity type formed in said substrate, a channel region (13) formed in the surface region of said substrate and located between said first and second diffusion layers, a floating gate electrode (14) formed on said channel region, a control gate electrode (15) formed on said floating gate electrode, and means (16) for lessening an electric field concentration which occurs between said first layer and said channel region; a control gate line (CG) for supplying predetermined voltages to said control gate electrode, in a read mode and in a write mode; a read line (RL) for supplying predetermined voltages to said first diffusion layer, in the read mode and in the write mode; and a write line (WL) for supplying predetermined voltages to said second diffusion layer, in the read mode and in the write mode.
Claim 3
Dependent Claim
116 words
The memory device according to claim 1, characterized in that said write line (WL) supplies a first voltage to said second diffusion layer, in the write mode, and a second voltage, lower than said first voltage, to said second diffusion layer, in the read mode, said control gate line (CG) supplies said first voltage to said control gate electrode in the write mode, and a third voltage, lower than said first voltage but higher than said second voltage, to said control gate electrode, in the read mode, and said read line (RL) supplies said second voltage to said first diffusion layer, in the write mode, and said third voltage to the same, in the read mode.
Claim 4
Dependent Claim
56 words
The memory device according to claim 1, characterized in that said means for lessening an electric field concentration includes a third diffusion layer (17) of the second conductivity type, at a lower impurity concentration than that of said first diffusion layer, said third diffusion layer being formed between said first diffusion layer and said channel region.
Claim 5
Dependent Claim
51 words
The memory device according to claim 1, characterized in that said means for lessening an electric field concentration includes a third diffusion layer (18) of the second conductivity type, at a lower impurity concentration than that of said first diffusion layer, said fourth diffusion layer (18) surrounding said first diffusion layer.
Claim 6
Dependent Claim
53 words
The memory device according to claim 2, characterized by further comprising a load circuit (40) and a sense amplifier circuit (33), and characterized in that said read line (RL) is connected to a power source via said load circuit, and a signal on said read line is supplied to said sense amplifier circuit.
Claim 7
Dependent Claim
26 words
The memory device according to claim 5, characterized in that said load circuit (40) includes a MOS transistor which is conductive only in the read mode.
Claim 8
Dependent Claim
28 words
The memory device according to claim 5, characterized in that said load circuit (40) includes a MOS transistor having a conduction which is controlled by a clock signal.
Claim 9
Dependent Claim
19 words
The memory device according to claim 5, characterized in that said sense amplifier circuit (33) includes an inverter circuit.
Claim 10
Dependent Claim
174 words
A nonvolatile semiconductor memory device comprising: a memory cell (20) including a first conductivity type semiconductor substrate (10), first and second diffusion layers (11, 12) of a second conductivity type formed in said substrate, a channel region (13) formed in the surface region of said substrate and located between said first and second diffusion layers, a floating gate electrode (14) formed on said channel region, a control gate electrode (15) formed on said floating gate electrode, and carrier injection-preventing means (16) for preventing the carriers generated in the vicinity of said first diffusion layer in said channel region from being injected into said floating gate electrode; a control gate line (CG) for supplying predetermined voltages to said control gate electrode, in a read mode and in a write mode; a read line (RL) for supplying predetermined voltages to said first diffusion layer, in the read mode and in the write mode; and a write line (WL) for supplying predetermined voltages to said second diffusion layer, in the read mode and in the write mode.
Claim 11
Dependent Claim
174 words
A nonvolatile semiconductor memory device comprising: a memory cell (20) including a first conductivity type semiconductor substrate (10), first and second diffusion layers (11, 12) of a second conductivity type formed in said substrate, a channel region (13) formed in the surface region of said substrate and located between said first and second diffusion layers, a floating gate electrode (14) formed on said channel region, a control gate electrode (15) formed on said floating gate electrode, and carrier injection-preventing means (16) for preventing the carriers generated in the vicinity of said first diffusion layer in said channel region from being injected into said floating gate electrode; a control gate line (CG) for supplying predetermined voltages to said control gate electrode, in a read mode and in a write mode; a read line (RL) for supplying predetermined voltages to said first diffusion layer, in the read mode and in the write mode; and a write line (WL) for supplying predetermined voltages to said second diffusion layer, in the read mode and in the write mode.
Claim 12
Dependent Claim
116 words
The memory device according to claim 9, characterized in that said write line (WL) supplies a first voltage to said second diffusion layer, in the write mode, and a second voltage, lower than said first voltage, to said second diffusion layer, in the read mode, said control gate (CG) line supplies said first voltage to said control gate electrode, in the write mode, and a third voltage, lower than said first voltage but higher than said second voltage, to said control gate electrode, in the read mode, and said read line (RL) supplies said second voltage to said first diffusion layer, in the write mode, and said third voltage to the same, in the read mode.
Claim 13
Dependent Claim
58 words
The memory device according to claim 9, characterized in that said carrier injection-preventing means (16) is an insulating film (19) formed between said floating gate and a portion of the substrate surface in which the junction of said first diffusion layer and said channel region is exposed, and prevents carriers from being injected into said floating gate electrode.
Claim 14
Dependent Claim
39 words
The memory device according to claim 9, characterized in that said carrier injection-preventing means (16) is a portion of said control gate and extends above the channel region surface lying between said first diffusion layer and said floating gate.
Claim 15
Dependent Claim
53 words
The memory device according to claim 10, characterized by further comprising a load circuit (40) and a sense amplifier circuit (33), and characterized in that said read line (RL) is connected to a power source via said load circuit, and a signal on said read line is supplied to said sense amplifier circuit.
Claim 16
Dependent Claim
26 words
The memory device according to claim 13, characterized in that said load circuit (40) includes a MOS transistor which is conductive only in the read mode.
Claim 17
Dependent Claim
28 words
The memory device according to claim 13, characterized in that said load circuit (40) includes a MOS transistor having a conduction which is controlled by a clock signal.
Claim 18
Dependent Claim
19 words
The memory device according to claim 13, characterized in that said sense amplifier circuit (33) includes an inverter circuit.
References Cited (Backward Citations)
No citation records indexed.
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