US4651406A
Expired / Lapsed
US
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Forming memory transistors with varying gate oxide thicknesses
Assignee: Hitachi Ltd
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Filing: 1986-06-04
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Granted: 1987-03-24
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Expires: 2006-06-04
Abstract
Abstract A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.
Inventors
- 👤 Shinji Shimizu
- 👤 Kazuhiro Komori
- 👤 Yasunobu Kosa
- 👤 June Sugiura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:05
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/49; H10D; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0158; H10P; H10P14/00; H10P14/60; H10P14/61
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
297 words
A method of manufacturing a semiconductor integrated circuit device comprising first type MIS transistors capable of operating at high voltage and second type MIS transistors, capable of operating at low voltage, comprising the steps of: (a) preparing a semiconductor substrate having a first conductivity type region, said first conductivity type region having a major surface; (b) forming an insulating region dividing said major surface into first and second areas on which to form said first type MIS transistors and said second type MIS transistors, respectively; (c) introducing an impurity of the same conductivity type as the conductivity type of said first conductivity type region into said second area through an insulating film formed over the second area without introducing said impurity into said first area; (d) introducing an impurity of the same conductivity type as the conductivity type of said first conductivity type region into said first and second areas simultaneously through an insulating film, serving as a gate insulating film, formed over the first and second areas so as to have a thin thickness portion over said second area and a thick thickness portion over said first area; (e) forming a plurality of gate electrodes on said insulating film serving as the gate insulating film so as to exist over each of said first and second areas; and (f) forming source and drain regions associated with each of said plurality of gate electrodes in said first and second areas by introducing an impurity of the opposite conductivity type to the conductivity type of said first conductivity type region into said first and second areas, said plurality of source and drain regions forming said first type MIS transistors and said second type MIS transistors with said plurality of gate electrodes in said first and second areas, respectively.
Claim 2
Independent Claim
297 words
A method of manufacturing a semiconductor integrated circuit device comprising first type MIS transistors capable of operating at high voltage and second type MIS transistors, capable of operating at low voltage, comprising the steps of: (a) preparing a semiconductor substrate having a first conductivity type region, said first conductivity type region having a major surface; (b) forming an insulating region dividing said major surface into first and second areas on which to form said first type MIS transistors and said second type MIS transistors, respectively; (c) introducing an impurity of the same conductivity type as the conductivity type of said first conductivity type region into said second area through an insulating film formed over the second area without introducing said impurity into said first area; (d) introducing an impurity of the same conductivity type as the conductivity type of said first conductivity type region into said first and second areas simultaneously through an insulating film, serving as a gate insulating film, formed over the first and second areas so as to have a thin thickness portion over said second area and a thick thickness portion over said first area; (e) forming a plurality of gate electrodes on said insulating film serving as the gate insulating film so as to exist over each of said first and second areas; and (f) forming source and drain regions associated with each of said plurality of gate electrodes in said first and second areas by introducing an impurity of the opposite conductivity type to the conductivity type of said first conductivity type region into said first and second areas, said plurality of source and drain regions forming said first type MIS transistors and said second type MIS transistors with said plurality of gate electrodes in said first and second areas, respectively.
Claim 3
Dependent Claim
32 words
A method of manufacturing a semiconductor integrated circuit device as defined in claim 1, wherein said insulating region is formed by oxidation of said main surface of the first conductivity type region.
Claim 4
Dependent Claim
24 words
A method of manufacturing a semiconductor integrated circuit device as defined in claim 1, wherein said impurity is introduced by an ion implantation process.
Claim 5
Dependent Claim
27 words
A method of manufacturing a semiconductor integrated circuit device as defined in claim 1, wherein said plurality of gate electrodes are formed from a high-melting point metal.
Claim 6
Dependent Claim
27 words
A method of manufacturing a semiconductor integrated circuit device as defined in claim 1, wherein said plurality of gate electrodes are formed from a polycrystalline silicon layer.
Claim 7
Dependent Claim
310 words
In a method of manufacturing a semiconductor integrated circuit device comprising preparing a first conductivity type region having a major surface; forming an insulating region dividing said major surface into a first area and a second area; and forming a plurality of MIS type transistors in said first area and in said second area, said plurality of MIS type transistors including first type MIS transistors capable of operating at high voltage formed in said first area and second type MIS transistors capable of operating at low voltage formed in said second area, the improvement comprising the steps of: (a) introducing an impurity of the same conductivity type as the conductivity type of said first conductivity type region into said second area through an insulating film formed over the second area without introducing said impurity into said first area; (b) introducing an impurity of the same conductivity type as the conductivity type of said first conductivity type region into said first and second areas simultaneously through an insulating film, serving as a gate insultating film, formed over the first and second areas so as to have a thin thickness portion over said second area and a thick thickness portion over said first area; (c) forming a plurality of gate electrodes on said insulating film serving as the gate insulating film so as to exist over each of said first and second areas; and (d) forming source and drain regions associated with each of said plurality of gate electrodes in said first and second areas by introducing an impurity of the opposite conductivity type to the conductivity type of said first conductivity type region into said first and second areas, said plurality of source and drain regions forming said first type MIS transistors and said second type MIS transistors with said plurality of gate electrodes and said first and second areas, respectively.
Claim 8
Dependent Claim
310 words
In a method of manufacturing a semiconductor integrated circuit device comprising preparing a first conductivity type region having a major surface; forming an insulating region dividing said major surface into a first area and a second area; and forming a plurality of MIS type transistors in said first area and in said second area, said plurality of MIS type transistors including first type MIS transistors capable of operating at high voltage formed in said first area and second type MIS transistors capable of operating at low voltage formed in said second area, the improvement comprising the steps of: (a) introducing an impurity of the same conductivity type as the conductivity type of said first conductivity type region into said second area through an insulating film formed over the second area without introducing said impurity into said first area; (b) introducing an impurity of the same conductivity type as the conductivity type of said first conductivity type region into said first and second areas simultaneously through an insulating film, serving as a gate insultating film, formed over the first and second areas so as to have a thin thickness portion over said second area and a thick thickness portion over said first area; (c) forming a plurality of gate electrodes on said insulating film serving as the gate insulating film so as to exist over each of said first and second areas; and (d) forming source and drain regions associated with each of said plurality of gate electrodes in said first and second areas by introducing an impurity of the opposite conductivity type to the conductivity type of said first conductivity type region into said first and second areas, said plurality of source and drain regions forming said first type MIS transistors and said second type MIS transistors with said plurality of gate electrodes and said first and second areas, respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-23 | 1990-09-22 | 1991-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-23 | 1994-09-22 | 1995-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-23 | 1998-09-22 | 1999-03-24 | $7700.00 | Window Closed / Lapsed |