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JPS60110171A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor memory

Assignee: Toshiba Corp
•
Filing: 1983-11-21
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Granted: —
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Expires: 2003-11-21
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Abstract

Abstract PURPOSE:To simplify the manufacturing steps by forming a low density diffused layer near a channel region only in one of the regions to become source and drain regions of a memory cell. CONSTITUTION:A gate electrode 43 made of a control gate electrode 56 and a floating gate electrode 54 of an EPROM cell and gate electrodes 44, 58 of an MOS transistor are formed to cross perpendicularly to each other. High dosage ion implantation is performed oblique from above in parallel with the gate longitudinal direction of the electrode 56 and low dosage ion implantation is performed vertically directly from above to provide a low density (n type) diffused layer 59a near the channel region only in one of the regions to become source and drain regions of the EPROM cell and hence the region 59. Thus, the EPROM cell for effectively preventing the erroneous readout and the normal MOS transistor are formed in an extremely simple steps.

Inventors

  • 👤 Yoshihide Nagakubo
  • 👤 長久保 吉秀
  • 👤 Yoshihisa Mizutani
  • 👤 水谷 嘉久

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 00:10
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685

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