US5340760A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing EEPROM memory device
Assignee: Samsung Electronics Co Ltd
•
Filing: 1992-12-15
•
Granted: 1994-08-23
•
Expires: 2012-12-15
Abstract
Abstract This invention discloses EEPROM which increases an erasing voltage V pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.
Inventors
- 👤 Kazuhiro Komori
- 👤 Satoshi Meguro
- 👤 Takaaki Hagiwara
- 👤 Hitoshi Kume
- 👤 Toshihisa Tsukada
- 👤 Hideaki Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:10
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D30/686; H10D88/00
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
528 words
A method of manufacturing a semiconductor memory device, said semiconductor memory device comprising a memory cell and an MISFET for a peripheral circuit, said method comprising steps of: providing a semiconductor substrate of a first conductivity type having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film formed on said memory cell forming region, a floating gate electrode formed on said first gate insulating film, a second gate insulating film formed on said floating gate electrode, and a control gate electrode formed on said second gate insulating film, and with a third gate insulating film formed on said peripheral circuit forming region, and a first gate electrode of said MISFET formed on said third gate insulating film; forming a first semiconductor region, of a second conductivity type, in said memory cell forming region, by introducing in said memory cell forming region an impurity in self-alignment with one end portion of said control gate electrode; forming a second semiconductor region, of said second conductivity type, in said memory cell forming region, by introducing in said memory cell forming region an impurity in self-alignment with another end portion of said control gate electrode, wherein a junction depth of said first semiconductor region is greater than a junction depth of said second semiconductor region; forming a third semiconductor region, of said first conductivity type, in said memory cell forming region, by introducing in said memory cell forming region an impurity in self-alignment with said another end portion of said control gate electrode, wherein a junction depth of said third semiconductor region is greater than a junction depth of said second semiconductor region, and wherein an impurity concentration of said third semiconductor region is higher than an impurity concentration of said semiconductor substrate; forming a fourth semiconductor region, of said second conductivity type, in said peripheral circuit forming region, by introducing in said peripheral circuit forming region an impurity in self-alignment with said first gate electrode, wherein an impurity concentration of said first semiconductor region is higher than an impurity concentration of said fourth semiconductor region; after the steps of forming first, second, third, and fourth semiconductor regions, forming first side wall spacers on both side surfaces of said control and floating gate electrodes in self-alignment with said control and floating gate electrode, and forming second side wall spacers on both side surfaces of said first gate electrode in self-alignment with said first gate electrode; and forming a fifth semiconductor region, of said second conductivity type, in said peripheral circuit forming region by introducing in said peripheral circuit forming region an impurity, in self-alignment with said second side wall spacers, wherein an impurity concentration of said fifth semiconductor region is higher than the impurity concentration of said fourth semiconductor region, and wherein said fourth and fifth semiconductor regions serve as a drain region of said MISFET, wherein data is stored in said memory cell by injecting hot-carriers into said floating gate electrode, and wherein data is erased from said memory cell by emitting said injected carriers from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film.
Claim 2
Independent Claim
528 words
A method of manufacturing a semiconductor memory device, said semiconductor memory device comprising a memory cell and an MISFET for a peripheral circuit, said method comprising steps of: providing a semiconductor substrate of a first conductivity type having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film formed on said memory cell forming region, a floating gate electrode formed on said first gate insulating film, a second gate insulating film formed on said floating gate electrode, and a control gate electrode formed on said second gate insulating film, and with a third gate insulating film formed on said peripheral circuit forming region, and a first gate electrode of said MISFET formed on said third gate insulating film; forming a first semiconductor region, of a second conductivity type, in said memory cell forming region, by introducing in said memory cell forming region an impurity in self-alignment with one end portion of said control gate electrode; forming a second semiconductor region, of said second conductivity type, in said memory cell forming region, by introducing in said memory cell forming region an impurity in self-alignment with another end portion of said control gate electrode, wherein a junction depth of said first semiconductor region is greater than a junction depth of said second semiconductor region; forming a third semiconductor region, of said first conductivity type, in said memory cell forming region, by introducing in said memory cell forming region an impurity in self-alignment with said another end portion of said control gate electrode, wherein a junction depth of said third semiconductor region is greater than a junction depth of said second semiconductor region, and wherein an impurity concentration of said third semiconductor region is higher than an impurity concentration of said semiconductor substrate; forming a fourth semiconductor region, of said second conductivity type, in said peripheral circuit forming region, by introducing in said peripheral circuit forming region an impurity in self-alignment with said first gate electrode, wherein an impurity concentration of said first semiconductor region is higher than an impurity concentration of said fourth semiconductor region; after the steps of forming first, second, third, and fourth semiconductor regions, forming first side wall spacers on both side surfaces of said control and floating gate electrodes in self-alignment with said control and floating gate electrode, and forming second side wall spacers on both side surfaces of said first gate electrode in self-alignment with said first gate electrode; and forming a fifth semiconductor region, of said second conductivity type, in said peripheral circuit forming region by introducing in said peripheral circuit forming region an impurity, in self-alignment with said second side wall spacers, wherein an impurity concentration of said fifth semiconductor region is higher than the impurity concentration of said fourth semiconductor region, and wherein said fourth and fifth semiconductor regions serve as a drain region of said MISFET, wherein data is stored in said memory cell by injecting hot-carriers into said floating gate electrode, and wherein data is erased from said memory cell by emitting said injected carriers from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film.
Claim 3
Dependent Claim
111 words
A method of manufacturing a semiconductor memory device according to claim 1, further comprising the step of: forming a first mask layer which is formed over a first portion, in said memory cell forming region, where said first semiconductor region is to be formed, wherein said first mask layer has a first opening which exposes a second portion, in said memory cell forming region, where said third semiconductor region is to be formed, wherein, in the step of forming the third semiconductor region, said impurity introduced in forming said third semiconductor region is introduced in said second portion through said first opening by using said first mask layer as a mask.
Claim 4
Dependent Claim
23 words
A method of manufacturing a semiconductor memory device according to claim 2, wherein said first mask layer covers said peripheral circuit forming region.
Claim 5
Dependent Claim
118 words
A method of manufacturing a semiconductor memory device according to claim 2, wherein said first mask layer covers said peripheral circuit forming region, and wherein said first mask layer further has a second opening which exposes a third portion, in said peripheral circuit forming region, where said drain region of said MISFET is to be formed, and wherein, in the step of forming the third semiconductor region, said impurity introduced in forming said third semiconductor region is introduced in said third portion through said second opening by using said first mask layer as a mask, whereby a sixth semiconductor region of said first conductivity type is formed at a drain edge of said drain region of said MISFET.
Claim 6
Dependent Claim
111 words
A method of manufacturing a semiconductor memory device according to claim 1, further comprising the step of: forming a second mask layer which is formed over a fourth portion, in said memory cell forming region, where said first semiconductor region is to be formed, wherein said second mask layer has a third opening which exposes a fifth portion, in said memory cell forming region, where said second semiconductor region is to be formed, wherein, in the step of forming the second semiconductor region, said impurity introduced in forming the second semiconductor region is introduced in said fifth portion through said third opening by using said second mask layer as a mask.
Claim 7
Dependent Claim
107 words
A method of manufacturing a semiconductor memory device according to claim 1, wherein, in the step of forming the fifth. semiconductor region, said impurity introduced in forming the fifth semiconductor region is introduced in both said peripheral circuit forming region and said memory cell forming region, and is introduced in self-alignment with said first side wall spacers in said memory cell forming region, whereby seventh semiconductor regions of said second conductivity type are formed in said memory cell forming region, and wherein an impurity concentration of said seventh semiconductor regions is higher than an impurity concentration of said second semiconductor region and of said first semiconductor region.
Claim 8
Dependent Claim
32 words
A method of manufacturing a semiconductor memory device according to claim 6, wherein the junction depth of said third semiconductor region is greater than a junction depth of said seventh semiconductor regions.
Claim 9
Dependent Claim
32 words
A method of manufacturing a semiconductor memory device according to claim 6, wherein a junction depth of said seventh semiconductor regions is greater than the junction depth of said third semiconductor region.
Claim 10
Dependent Claim
175 words
(Amended) A method of manufacturing a semiconductor memory device according to claim 1, wherein said first semiconductor region includes a first subregion and a second subregion, wherein said first subregion is formed between said second subregion and a channel forming region, wherein an impurity concentration of said first subregion is lower than an impurity concentration of said second subregion, wherein said first subregion has a junction depth greater than that of said second subregion so as to surround said second subregion, wherein, in the step of forming the fifth semiconductor region, said impurity introduced in forming the fifth semiconductor region is introduced in both said peripheral circuit forming region and memory cell forming region, and is introduced in self-alignment with said first side wall spacers in said memory cell forming region, whereby seventh semiconductor regions of said second conductivity type are formed in said memory cell forming region, and wherein an impurity concentration of said seventh semiconductor regions is higher than the impurity concentration of said first semiconductor region and of said second semiconductor region,
Claim 11
Dependent Claim
31 words
A method of manufacturing a semiconductor memory device according to claim 9, wherein a junction depth of said seventh semiconductor regions is greater than the junction depth of said first subregion,
Claim 12
Dependent Claim
31 words
A method of manufacturing a semiconductor memory device according to claim 26, wherein the junction depth of said first subregion is greater than a junction depth of said seventh semiconductor regions,
Claim 13
Dependent Claim
32 words
A method of manufacturing a semiconductor memory device according to claim 9, wherein the junction depth of said third semiconductor region is greater than a junction depth of said seventh semiconductor regions.
Claim 14
Dependent Claim
32 words
A method of manufacturing a semiconductor memory device according to claim 9, wherein a junction depth of said seventh semiconductor regions is greater than the junction depth of said third semiconductor region.
Claim 15
Independent Claim
435 words
A method of manufacturing a semiconductor memory device, said semiconductor memory device comprising a memory cell and an MISFET for a peripheral circuit, said method comprising steps of: providing a semiconductor substrate of a first conductivity type having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film formed on said memory cell forming region, a floating gate electrode formed on said first gate insulating film, a second gate insulating film formed on said floating gate electrode, and a control gate electrode formed on said second gate insulating film, and with a third gate insulating film formed on said peripheral circuit forming region, and a first gate electrode of said MISFET formed on said third gate insulating film; forming a first semiconductor region of a second conductivity type in said memory cell forming region, by introducing in said memory cell forming region an impurity in self-alignment with one end portion of said control gate electrode; forming a second semiconductor region of said second conductivity type, in said memory cell forming region, by introducing in said memory cell forming region an impurity in self-alignment with another end portion of said control gate electrode, wherein the junction depth of said first semiconductor region is greater than the junction depth of said second semiconductor region; forming fourth semiconductor regions of said second conductivity type, in said peripheral circuit forming region, by introducing in said peripheral circuit forming region an impurity in self-alignment with both end portions of said first gate electrode, wherein an impurity concentration of said first semiconductor region is higher than an impurity concentration of said fourth semiconductor regions; after the steps of forming first, second, and fourth semiconductor regions, forming first side wall spacers on both side surfaces of said control and floating gate electrodes in self-alignment with said control and floating gate electrodes, and forming second side wall spacers on both side surfaces of said first gate electrode in self-alignment with said first gate electrode; and forming fifth semiconductor regions of said second conductivity type in said peripheral circuit forming region by introducing an impurity, in self-alignment with said second side wall spacers, in said peripheral circuit forming region, wherein the impurity concentration of said fifth semiconductor regions is higher than the impurity concentration of said fourth semiconductor regions, wherein data is stored in said memory cell by injecting hot-carriers into said floating gate electrode, and wherein data is erased from said memory cell by emitting said injected carriers from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film.
Claim 16
Independent Claim
435 words
A method of manufacturing a semiconductor memory device, said semiconductor memory device comprising a memory cell and an MISFET for a peripheral circuit, said method comprising steps of: providing a semiconductor substrate of a first conductivity type having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film formed on said memory cell forming region, a floating gate electrode formed on said first gate insulating film, a second gate insulating film formed on said floating gate electrode, and a control gate electrode formed on said second gate insulating film, and with a third gate insulating film formed on said peripheral circuit forming region, and a first gate electrode of said MISFET formed on said third gate insulating film; forming a first semiconductor region of a second conductivity type in said memory cell forming region, by introducing in said memory cell forming region an impurity in self-alignment with one end portion of said control gate electrode; forming a second semiconductor region of said second conductivity type, in said memory cell forming region, by introducing in said memory cell forming region an impurity in self-alignment with another end portion of said control gate electrode, wherein the junction depth of said first semiconductor region is greater than the junction depth of said second semiconductor region; forming fourth semiconductor regions of said second conductivity type, in said peripheral circuit forming region, by introducing in said peripheral circuit forming region an impurity in self-alignment with both end portions of said first gate electrode, wherein an impurity concentration of said first semiconductor region is higher than an impurity concentration of said fourth semiconductor regions; after the steps of forming first, second, and fourth semiconductor regions, forming first side wall spacers on both side surfaces of said control and floating gate electrodes in self-alignment with said control and floating gate electrodes, and forming second side wall spacers on both side surfaces of said first gate electrode in self-alignment with said first gate electrode; and forming fifth semiconductor regions of said second conductivity type in said peripheral circuit forming region by introducing an impurity, in self-alignment with said second side wall spacers, in said peripheral circuit forming region, wherein the impurity concentration of said fifth semiconductor regions is higher than the impurity concentration of said fourth semiconductor regions, wherein data is stored in said memory cell by injecting hot-carriers into said floating gate electrode, and wherein data is erased from said memory cell by emitting said injected carriers from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film.
Claim 17
Dependent Claim
174 words
A method of manufacturing a semiconductor memory device according to claim 14, wherein said first semiconductor region includes a first subregion and a second subregion, wherein said first subregion is formed between said second subregion and a channel forming region, wherein the impurity concentration of said first subregion is lower than the impurity concentration of said second subregion, wherein said first subregion has a junction depth greater than that of said second subregion so as to surround said second subregion, wherein, in the step of forming the fifth semiconductor region, said impurity introduced in forming the fifth semiconductor region is introduced in both said peripheral circuit forming region and said memory cell forming region, and is introduced in self-alignment with said first side wall spacers in said memory cell forming regions, whereby seventh semiconductor regions of said second conductivity type are formed in said memory cell forming region, and wherein an impurity concentration of said seventh semiconductor regions is higher than the impurity concentration of said first semiconductor region and said second semiconductor region.
Claim 18
Dependent Claim
31 words
A method of manufacturing a semiconductor memory device according to claim 15, wherein the junction depth of said seventh semiconductor regions is greater than the junction depth of said first subregion.
Claim 19
Dependent Claim
31 words
A method of manufacturing a semiconductor memory device according to claim 15, wherein the junction depth of said first subregion is greater than the junction depth of said seventh semiconductor regions.
Claim 20
Dependent Claim
29 words
A method of manufacturing a semiconductor memory device according to claim 15, wherein forming said first subregion and forming said second semiconductor region are performed in a common step.
Claim 21
Independent Claim
526 words
A method of manufacturing a semiconductor memory device, said semiconductor memory device comprising a memory cell and an MISFET for a peripheral circuit, said method comprising steps of: providing a semiconductor substrate of a first conductivity type having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film formed on said memory cell forming region, a floating gate electrode formed on said first gate insulating film, a second gate insulating film formed on said floating gate electrode, and a control gate electrode formed on said second gate insulating film, and with a third gate insulating film formed on said peripheral circuit forming region, and a first gate electrode of said MISFET formed on said third gate insulating film; forming first and second semiconductor regions, of a second conductivity type, in said memory cell forming region, by introducing in said memory cell forming region an impurity in self-alignment with both end portions of said control gate electrode, wherein a channel forming region is formed, in said memory cell forming region, between said first and second semiconductor regions; forming a third semiconductor region, of said first conductivity type, in said memory cell forming region by introducing in said memory cell forming region an impurity in self-alignment with one end portion of said control gate electrode, wherein a junction depth of said third semiconductor region is greater than a junction depth of said second semiconductor region, and wherein an impurity concentration of said third semiconductor region is higher than an impurity concentration of said semiconductor substrate; forming fourth semiconductor regions, of said second conductivity type, in said peripheral circuit forming region by introducing in said peripheral circuit forming region an impurity in self-alignment with both end portions of said first gate electrode, wherein the impurity concentration of said fourth semiconductor regions is lower than the impurity concentration of said first semiconductor region; after the steps of forming first and second, third, and fourth semiconductor regions, forming first side wall spacers on both side surfaces of said control and floating gate electrodes in self-alignment with said control and floating gate electrodes, and forming second side wall spacers on both side surfaces of said first gate electrode in self-alignment with said first gate electrode; and forming fifth semiconductor regions, of said second conductivity type, in said peripheral circuit forming region, and forming seventh semiconductor regions, of said second conductivity type, in said memory cell forming region, by introducing an impurity in both said peripheral circuit forming region and memory cell forming region in self-alignment with said first and second side wall spacers, wherein an impurity concentration of said fifth and seventh semiconductor regions is higher than the impurity concentration of said first and second semiconductor regions, and wherein a junction depth of said fifth and seventh semiconductor regions is greater than the junction depth of said first and second semiconductor regions, and wherein carriers in said floating gate electrode are emitted from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film, and wherein said second semiconductor region serves as a drain region in a read operation.
Claim 22
Independent Claim
526 words
A method of manufacturing a semiconductor memory device, said semiconductor memory device comprising a memory cell and an MISFET for a peripheral circuit, said method comprising steps of: providing a semiconductor substrate of a first conductivity type having a memory cell forming region and a peripheral circuit forming region, with a first gate insulating film formed on said memory cell forming region, a floating gate electrode formed on said first gate insulating film, a second gate insulating film formed on said floating gate electrode, and a control gate electrode formed on said second gate insulating film, and with a third gate insulating film formed on said peripheral circuit forming region, and a first gate electrode of said MISFET formed on said third gate insulating film; forming first and second semiconductor regions, of a second conductivity type, in said memory cell forming region, by introducing in said memory cell forming region an impurity in self-alignment with both end portions of said control gate electrode, wherein a channel forming region is formed, in said memory cell forming region, between said first and second semiconductor regions; forming a third semiconductor region, of said first conductivity type, in said memory cell forming region by introducing in said memory cell forming region an impurity in self-alignment with one end portion of said control gate electrode, wherein a junction depth of said third semiconductor region is greater than a junction depth of said second semiconductor region, and wherein an impurity concentration of said third semiconductor region is higher than an impurity concentration of said semiconductor substrate; forming fourth semiconductor regions, of said second conductivity type, in said peripheral circuit forming region by introducing in said peripheral circuit forming region an impurity in self-alignment with both end portions of said first gate electrode, wherein the impurity concentration of said fourth semiconductor regions is lower than the impurity concentration of said first semiconductor region; after the steps of forming first and second, third, and fourth semiconductor regions, forming first side wall spacers on both side surfaces of said control and floating gate electrodes in self-alignment with said control and floating gate electrodes, and forming second side wall spacers on both side surfaces of said first gate electrode in self-alignment with said first gate electrode; and forming fifth semiconductor regions, of said second conductivity type, in said peripheral circuit forming region, and forming seventh semiconductor regions, of said second conductivity type, in said memory cell forming region, by introducing an impurity in both said peripheral circuit forming region and memory cell forming region in self-alignment with said first and second side wall spacers, wherein an impurity concentration of said fifth and seventh semiconductor regions is higher than the impurity concentration of said first and second semiconductor regions, and wherein a junction depth of said fifth and seventh semiconductor regions is greater than the junction depth of said first and second semiconductor regions, and wherein carriers in said floating gate electrode are emitted from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film, and wherein said second semiconductor region serves as a drain region in a read operation.
Claim 23
Dependent Claim
32 words
A method of manufacturing a semiconductor memory device according to claim 19, wherein the junction depth of said seventh semiconductor regions is greater than the junction depth of said third semiconductor region.
Claim 24
Dependent Claim
107 words
A method of manufacturing a semiconductor memory device according to claim 20, further comprising the step of: before the step of forming said first and second side wall spacers, forming an eighth semiconductor region, of said second conductivity type, in said memory cell forming region by introducing in said memory cell forming region an impurity in self-alignment with an end portion of said control gate electrode, wherein the junction depth of said seventh semiconductor regions is greater than a junction depth of said eighth semiconductor region, and wherein the impurity concentration of said first semiconductor region is higher than an impurity concentration of said eighth semiconductor region.
Claim 25
Dependent Claim
104 words
A method of manufacturing a semiconductor memory device according to claim 19, further comprising the step of: forming a third mask layer which is formed over said memory cell forming region and peripheral circuit forming region, wherein said third mask layer has a fourth opening which exposes a sixth portion, in said memory cell forming region, where said third semiconductor region is to be formed, and wherein, in the step of forming the third semiconductor region, said impurity introduced in forming the third semiconductor region is introduced into said sixth portion through said fourth opening by using said third mask layer as a mask.
Claim 26
Dependent Claim
106 words
A method of manufacturing a semiconductor memory device according to claim 22, wherein said third mask layer further has a fifth opening which exposes a seventh portion, in said peripheral circuit forming region, where a drain region of said MISFET is to be formed, and wherein, in the step of forming the third semiconductor region, said impurity introduced in forming the third semiconductor region is introduced in said seventh portion through said fifth opening by using said third mask layer as a mask, whereby a sixth semiconductor region, of said first conductivity type, is formed at a drain edge of said drain region of said MISFET.
Claim 27
Dependent Claim
28 words
A method of manufacturing a semiconductor memory device according to claim 19, wherein said first conductivity type is p-type conductivity, and said second conductivity type is n-type conductivity.
Claim 28
Dependent Claim
28 words
A method of manufacturing a semiconductor memory device according to claim 14, wherein said first conductivity type is p-type conductivity, and said second conductivity type is n-type conductivity.
Claim 29
Dependent Claim
28 words
A method of manufacturing a semiconductor memory device according to claim 1, wherein said first conductivity type is p-type conductivity, and said second conductivity type is n-type conductivity.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-22 | 1998-02-21 | 1998-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-22 | 2002-02-21 | 2002-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-22 | 2006-02-21 | 2006-08-23 | $7700.00 | Window Closed / Lapsed |