US5625836A
Expired / Lapsed
US
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SIMD/MIMD processing memory element (PME)
Assignee: International Business Machines Corp
•
Filing: 1995-06-02
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Granted: 1997-04-29
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Expires: 2015-06-02
Abstract
Abstract A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.
Inventors
- 👤 Thomas N. Barker
- 👤 Clive A. Collins
- 👤 Michael C. Dapp
- 👤 James W. Dieffenderfer
- 👤 Donald M. Lesmeister
- 👤 Richard E. Nier
- 👤 Eric E. Retter
- 👤 Robert R. Richardson
- 👤 Vincent J. Smoral
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:45
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17337; G06F15/17343; G06F15/17356; G06F15/17368; G06F15/17381; G06F15/76; G06F15/80; G06F15/8007; G06F15/803; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3887; G06F9/3889
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
100 words
A multi-processor memory system, comprising: a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, each of said processing memory elements having a processor coupled with a dedicated local memory; means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein each dedicated local memory is independently accessible by the respectively coupled processor in both SIMD and MIMD modes exclusive of access by another processor.
Claim 2
Dependent Claim
100 words
A multi-processor memory system, comprising: a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, each of said processing memory elements having a processor coupled with a dedicated local memory; means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein each dedicated local memory is independently accessible by the respectively coupled processor in both SIMD and MIMD modes exclusive of access by another processor.
Claim 3
Dependent Claim
47 words
A multi-processor memory system according to claim 1 wherein there are plural copies of a processor embedded in a memory on the substrate which functions as a system node, and a means for changing under programmable control SIMD/MIMD functions as a multi-processor memory system at each node.
Claim 4
Dependent Claim
72 words
A multi-processor memory system according to claim 1 wherein each multi-processor memory element (PME) of the system is on a chip having multi-byte internal data flow and control; means for data and control communications; sufficient local storage for enabling MIMD local mode operation and data storage; circuit switched mode and store and forward mode; an on chip PME to PME communication network; and means for switching dynamically between SIMD and MIMD modes.
Claim 5
Dependent Claim
65 words
A multi-processor memory system according to claim 1 wherein each processor memory element comprises a 16-bit processing memory element with full 16-bit internal control and data flow for PME to PME communication within a network defined binary hypercube for said common substrate as a node, each node processor memory element having 16-bit internal data flow and control enabling high performance data manipulation and I/O operations.
Claim 6
Dependent Claim
53 words
A multi-processor memory system according to claim 1 having a 16 bit RISC ISA which permits decoded instructions to come from either internal memory via normal decode or from a broadcast bus connected in common to the multi-processor memory elements, thus permitting the mixture of SIMD and MIMD modes in the same machine.
Claim 7
Dependent Claim
35 words
A multi-processor memory system according to claim 1 further comprising within a processor memory element: means for dynamic switching between SIMD and MIMD modes of operation enabling dual SIMD/MIMD operation and group partitioned SIMD/MIMD operation.
Claim 8
Dependent Claim
44 words
A multi-processor memory system according to claim 1 further comprising within a processor memory element: means for dynamic switching between SIMD and MIMD modes of operation enabling dual SIMD/MIMD memory utilization for conversion routines and group partitioned SIMD/MIMD table value and fast fourier routines.
Claim 9
Dependent Claim
41 words
A multi-processor memory system according to claim 1 further comprising within a processor memory element: means for dynamic switching between SIMD and MIMD modes of operation for store and forward functions and circuit switched functions which enable message and data transferring.
Claim 10
Dependent Claim
31 words
A multi-processor memory system according to claim 1 further comprising within a processor memory element: means for switching between SIMD and MIMD modes of operation for fast fourier transform and sorting.
Claim 11
Dependent Claim
23 words
A multi-processor memory system according to claim 1 further comprising within a processor memory element: means for operating in SIMD or MIMD mode.
Claim 12
Dependent Claim
41 words
A multi-processor memory system according to claim 1 further comprising within a processing memory element: means for operating in SIMD or MIMD mode, and wherein a set of processor memory elements can be divided into subgroups that operate in different modes.
Claim 13
Dependent Claim
52 words
A multi-processor memory system according to claim 1 further comprising within a processing memory element: means for operating in SIMD or MIMD mode, and wherein a set of processor memory elements can be divided into subgroups that operate in different modes, with MIMD input groups, SIMD processing groups and MIMD output functions.
Claim 14
Dependent Claim
40 words
A multi-processor memory system according to claim 1 further comprising within a processing memory element: means for operating a processor memory element in MIMD mode and to switch between interrupt levels for managing input/output and routing functions associated with input/output.
Claim 15
Dependent Claim
67 words
A multi-processor memory system according to claim 1 wherein the processor of said processor memory element is a RISC processor with an instruction architecture which enables decoded instruction to originate from either internal memory via a normal instruction decode, or from a communication path functioning as a broadcast bus, and said instruction architecture enables a processor memory element to function in either SIMD mode or MIMD mode.
Claim 16
Dependent Claim
39 words
A multi-processor memory system according to claim 1 wherein the processor of said processor memory element is a RISC processor with an instruction architecture which enables a processor memory element to function in either SIMD mode or MIMD mode.
Claim 17
Dependent Claim
77 words
A multi-processor memory system according to claim 1 wherein a node forms part of a cluster, each node having a set of multiple processor memory elements, and wherein a complete set of processor memory element may be divided into 1 to many distinct subsets under control of an array director to interleave between subsets to operate distinct subsets of the array in one mode while other sets operate in tightly synchronized SIMD mode under array director control.
Claim 18
Dependent Claim
37 words
A multi-processor memory system according to claim 1 wherein a node processor memory element instruction decode logic permits the processor memory element to operate in either SIMD mode or MIMD mode, transitions between each mode occurring dynamically.
Claim 19
Dependent Claim
30 words
A multi-processor memory system according to claim 1 wherein a node processing memory element in SIMD mode receives decoded instruction information and executes that data in the next clock cycle.
Claim 20
Dependent Claim
37 words
A multi-processor memory system according to claim 1 wherein a node processing memory element in MIMD mode maintains a program counter PC address and uses that as the address within its own memory to fetch an instruction.
Claim 21
Dependent Claim
28 words
A multi-processor memory system according to claim 1 wherein a node processing memory element in SIMD mode enters MIMD mode when given information that represents a decode branch.
Claim 22
Dependent Claim
28 words
A multi-processor memory system according to claim 1 wherein a node processing memory element in MIMD mode enters SIMD mode upon executing a specific instruction for the transition.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-28 | 2000-10-28 | 2001-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-28 | 2004-10-28 | 2005-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-28 | 2008-10-28 | 2009-04-29 | $7700.00 | Window Closed / Lapsed |