US5570041A
Expired / Lapsed
US
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Programmable logic module and architecture for field programmable gate array device
Assignee: Microsemi SoC Corp
•
Filing: 1995-06-28
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Granted: 1996-10-29
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Expires: 2015-06-28
Abstract
Abstract A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.
Inventors
- 👤 Khaled A. El-Avat
- 👤 Sinan Kaptanoglu
- 👤 King W. Chan
- 👤 William C. Plants
- 👤 Jung-Cheun Lien
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:34
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516; G01R31/318519; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17724; H03K19/17728; H03K19/17736
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
181 words
A sequential logic unit comprising: a data flip-flop having a data input, a clock input, and an output; a first data multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input connected to a first control input conductor, and an output; a second data multiplexer having a first data input connected to the output of said data flip-flop, a second data input connected to said output of said first multiplexer, a control input, and an output connected to the data input of said data flip-flop; an output buffer having an input connected to said output of said data flip-flop output, and an output connected to an output conductor; and a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first and second multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements.
Claim 2
Dependent Claim
181 words
A sequential logic unit comprising: a data flip-flop having a data input, a clock input, and an output; a first data multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input connected to a first control input conductor, and an output; a second data multiplexer having a first data input connected to the output of said data flip-flop, a second data input connected to said output of said first multiplexer, a control input, and an output connected to the data input of said data flip-flop; an output buffer having an input connected to said output of said data flip-flop output, and an output connected to an output conductor; and a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first and second multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements.
Claim 3
Dependent Claim
45 words
The sequential logic unit of claim 1 further including: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to least some of said general interconnect conductors by user-programmable interconnect elements.
Claim 4
Dependent Claim
45 words
The sequential logic unit of claim 1 further including: a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said general interconnect conductors and connectable to least some of said general interconnect conductors by user-programmable interconnect elements.
Claim 5
Dependent Claim
404 words
A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output; a first logic gate having a first input connected to a fifth data input conductor, a second input connected to a sixth data input conductor and an output connected to the control inputs of said first and second multiplexers; a second logic gate having a first input connected to a seventh data input conductor, a second input connected to an eighth data input conductor and an output connected to the control input of said third multiplexer; a first output buffer having an input connected to said output of said third multiplexer and an output connected to a first output conductor; a data flip-flop having a data input, a clock input, and an output; a fourth data multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to a ninth data input conductor, a control input connected to a first control input conductor, and an output; a fifth data multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a second control input conductor, and an output connected to the data input of said data flip-flop; a second output buffer having an input connected to said output of said data flip-flop output, and an output connected to a second output conductor; and a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth and fifth multiplexers, said data flip-flop and said first and second output conductors of said first and second output buffers, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements.
Claim 6
Dependent Claim
404 words
A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output; a first logic gate having a first input connected to a fifth data input conductor, a second input connected to a sixth data input conductor and an output connected to the control inputs of said first and second multiplexers; a second logic gate having a first input connected to a seventh data input conductor, a second input connected to an eighth data input conductor and an output connected to the control input of said third multiplexer; a first output buffer having an input connected to said output of said third multiplexer and an output connected to a first output conductor; a data flip-flop having a data input, a clock input, and an output; a fourth data multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to a ninth data input conductor, a control input connected to a first control input conductor, and an output; a fifth data multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a second control input conductor, and an output connected to the data input of said data flip-flop; a second output buffer having an input connected to said output of said data flip-flop output, and an output connected to a second output conductor; and a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth and fifth multiplexers, said data flip-flop and said first and second output conductors of said first and second output buffers, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements.
Claim 7
Dependent Claim
49 words
The programmable logic module of claim 4 wherein said data flip-flop further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to least some of said general interconnect conductors by user-programmable interconnect elements.
Claim 8
Dependent Claim
49 words
The programmable logic module of claim 4 wherein said data flip-flop further includes: a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said general interconnect conductors and connectable to least some of said general interconnect conductors by user-programmable interconnect elements.
Claim 9
Dependent Claim
25 words
The programmable logic module of claim 4 wherein said first logic gate is an AND gate and said second logic gate is an OR gate.
Claim 10
Dependent Claim
14 words
The programmable logic module of claim 4 wherein said user-programmable interconnect elements are antifuses.
Claim 11
Dependent Claim
90 words
The programmable logic module of claim 4 further including an inverter having an input intersecting at least some of said plurality of general interconnect conductors and an output intersecting at least some of said plurality of general interconnect conductors and at least some of said first and second data inputs of said first and second multiplexers, said plurality of general interconnect conductors and said first and second data inputs of said first and second multiplexers selectively connectable to said input and said output of said inverter by user-programmable interconnect elements.
Claim 12
Dependent Claim
14 words
The programmable logic module of claim 9 wherein said user-programmable interconnect elements are antifuses.
Claim 13
Dependent Claim
476 words
A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output; a first logic gate having a first input connected to a fifth data input conductor, a second input connected to a sixth data input conductor and an output connected to the control inputs of said first and second multiplexers; a second logic gate having a first input connected to a seventh data input conductor, a second input connected to an eighth data input conductor and an output connected to the control input of said third multiplexer; a first output buffer having an input connected to said output of said third multiplexer and an output; a data flip-flop having a data input, a clock input, and an output; a fourth data multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to a ninth data input conductor, a control input connected to a first control input conductor, and an output; a fifth data multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a second control input conductor, and an output connected to the data input of said data flip-flop; a second output buffer having an input connected to said output of said data flip-flop output, and an output connected to an output conductor; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth and fifth multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; and a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to the output of said first output buffer, a second one of said local interconnect conductors connected to the output of said second output buffer, at least some of said local interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth and fifth multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements.
Claim 14
Dependent Claim
476 words
A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output; a first logic gate having a first input connected to a fifth data input conductor, a second input connected to a sixth data input conductor and an output connected to the control inputs of said first and second multiplexers; a second logic gate having a first input connected to a seventh data input conductor, a second input connected to an eighth data input conductor and an output connected to the control input of said third multiplexer; a first output buffer having an input connected to said output of said third multiplexer and an output; a data flip-flop having a data input, a clock input, and an output; a fourth data multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to a ninth data input conductor, a control input connected to a first control input conductor, and an output; a fifth data multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a second control input conductor, and an output connected to the data input of said data flip-flop; a second output buffer having an input connected to said output of said data flip-flop output, and an output connected to an output conductor; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth and fifth multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; and a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to the output of said first output buffer, a second one of said local interconnect conductors connected to the output of said second output buffer, at least some of said local interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth and fifth multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements.
Claim 15
Dependent Claim
49 words
The programmable logic module of claim 11 wherein said data flip-flop further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to least some of said general interconnect conductors by user-programmable interconnect elements.
Claim 16
Dependent Claim
49 words
The programmable logic module of claim 11 wherein said data flip-flop further includes: a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said general interconnect conductors and connectable to least some of said general interconnect conductors by user-programmable interconnect elements.
Claim 17
Dependent Claim
25 words
The programmable logic module of claim 11 wherein said first logic gate is an AND gate and said second logic gate is an OR gate.
Claim 18
Dependent Claim
14 words
The programmable logic module of claim 11 wherein said user-programmable interconnect elements are antifuses.
Claim 19
Dependent Claim
121 words
The programmable logic module of claim 11 further including an inverter having an input intersecting at least some of said plurality of general interconnect conductors and at least some of said local interconnect conductors and an output intersecting at least some of said plurality of general interconnect conductors, at least some of said local interconnect conductors and at least some of said first and second data inputs of said first and second multiplexers, said at least some of said plurality of general interconnect conductors, said at least some of said local interconnect conductors and said first and second data inputs of said first and second multiplexers selectively connectable to said input and said output of said inverter by user-programmable interconnect elements.
Claim 20
Dependent Claim
14 words
The programmable logic module of claim 16 wherein said user-programmable interconnect elements are antifuses.
Claim 21
Dependent Claim
620 words
A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output; a first logic gate having a first input connected to a fifth data input conductor, a second input connected to a sixth data input conductor and an output connected to the control inputs of said first and second multiplexers; a second logic gate having a first input connected to a seventh data input conductor, a second input connected to an eighth data input conductor and an output connected to the control input of said third multiplexer; a first output buffer having an input connected to said output of said third multiplexer and an output; a first data flip-flop having a data input, a clock input, and an output; a fourth data multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to a ninth data input conductor, a control input connected to a first control input conductor, and an output; a fifth data multiplexer having a first data input connected to the output of said first data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a second control input conductor, and an output connected to the data input of said first data flip-flop; a second output buffer having an input connected to said output of said first data flip-flop, and an output connected to an output conductor; a second data flip-flop having a data input, a clock input, and an output; a sixth data multiplexer having a first data input connected to a tenth data input conductor, a second data input connected to an eleventh data input conductor, a control input connected to a fourth control input conductor, and an output; a seventh data multiplexer having a first data input connected the output of said second data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a fifth control input conductor, and an output connected to the data input of said second data flip-flop; a third output buffer having an input connected to said output of said second data flip-flop, and an output connected to an output conductor; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth, fifth, sixth and seventh multiplexers and said first and second data flip-flops, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; and a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to the output of said first output buffer, a second one of said local interconnect conductors connected to the output of said second output buffer, at least some of said local interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth, fifth, sixth and seventh multiplexers and said first and second data flip-flops, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements.
Claim 22
Dependent Claim
620 words
A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output; a first logic gate having a first input connected to a fifth data input conductor, a second input connected to a sixth data input conductor and an output connected to the control inputs of said first and second multiplexers; a second logic gate having a first input connected to a seventh data input conductor, a second input connected to an eighth data input conductor and an output connected to the control input of said third multiplexer; a first output buffer having an input connected to said output of said third multiplexer and an output; a first data flip-flop having a data input, a clock input, and an output; a fourth data multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to a ninth data input conductor, a control input connected to a first control input conductor, and an output; a fifth data multiplexer having a first data input connected to the output of said first data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a second control input conductor, and an output connected to the data input of said first data flip-flop; a second output buffer having an input connected to said output of said first data flip-flop, and an output connected to an output conductor; a second data flip-flop having a data input, a clock input, and an output; a sixth data multiplexer having a first data input connected to a tenth data input conductor, a second data input connected to an eleventh data input conductor, a control input connected to a fourth control input conductor, and an output; a seventh data multiplexer having a first data input connected the output of said second data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a fifth control input conductor, and an output connected to the data input of said second data flip-flop; a third output buffer having an input connected to said output of said second data flip-flop, and an output connected to an output conductor; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth, fifth, sixth and seventh multiplexers and said first and second data flip-flops, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; and a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to the output of said first output buffer, a second one of said local interconnect conductors connected to the output of said second output buffer, at least some of said local interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth, fifth, sixth and seventh multiplexers and said first and second data flip-flops, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements.
Claim 23
Dependent Claim
56 words
The programmable logic module of claim 18 wherein at least one of said first and second data flip-flops further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to least some of said general interconnect conductors by user-programmable interconnect elements.
Claim 24
Dependent Claim
56 words
The programmable logic module of claim 18 wherein at least one of said first and second data flip-flops further includes: a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said general interconnect conductors and connectable to least some of said general interconnect conductors by user-programmable interconnect elements.
Claim 25
Dependent Claim
25 words
The programmable logic module of claim 18, wherein said first logic gate is an AND gate and said second logic gate is an OR gate.
Claim 26
Dependent Claim
15 words
The programmable logic module of claim 18 wherein said user programmable interconnect elements are antifuses.
Claim 27
Dependent Claim
121 words
The programmable logic module of claim 18 further including an inverter having an input intersecting at least some of said plurality of general interconnect conductors and at least some of said local interconnect conductors and an output intersecting at least some of said plurality of general interconnect conductors, at least some of said local interconnect conductors and at least some of said first and second data inputs of said first and second multiplexers, said at least some of said plurality of general interconnect conductors, said at least some of said local interconnect conductors and said first and second data inputs of said first and second multiplexers selectively connectable to said input and said output of said inverter by user-programmable interconnect elements.
Claim 28
Dependent Claim
14 words
The programmable logic module of claim 23 wherein said user-programmable interconnect elements are antifuses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-29 | 2000-04-29 | 2000-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-29 | 2004-04-29 | 2004-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-29 | 2008-04-29 | 2008-10-29 | $7700.00 | Window Closed / Lapsed |