Wafer level integrated circuit testing with a sacrificial metal layer

Abstract

Abstract A method and structure for wafer level testing of integrated circuit dice. A plurality of conductive paths are formed from a sacrificial metal layer and routed through the scribing lanes of the wafer. These conductive paths extend from selected I/O pads of the integrated circuit dice to an other portion of the wafer. Multiplexing and testing circuitry may also be formed on the wafer to facilitate integrated circuit testing. The novel method of the present invention further includes the step of removing the conductive paths before the wafer is segmented or otherwise operationally used. In one embodiment the conductive paths are formed from a conductive material differing from the conductive material used to form the I/O pads of the integrated circuits. Etching or heating may then preferentially remove the conductive paths prior to segmenting or otherwise operationally using the wafer. In an alternative embodiment an etching resistant mask is deposited over upper surfaces of the integrated circuit dice prior to the etching step. This mask protects the I/O pads and portions of the conductive paths overlapping the I/O pads. After the conductive paths have been removed by etching, the mask is also removed. In this embodiment the conductive paths may be formed from the same conductive material as the integrated circuit I/O pads.

Inventors

• 👤 Wilfred J. Corrigan

Bibliographic Details