US5289631A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for testing, burn-in, and/or programming of integrated circuit chips
Assignee: Amkor Technology Singapore Holding Pte Ltd
•
Filing: 1992-03-04
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Granted: 1994-03-01
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Expires: 2012-03-04
Abstract
Abstract An integrated circuit chip having solder bumps thereon may be tested using a temporary substrate having substrate pads corresponding to locations of the input/output pads on the chip and having a sacrificial conductor layer on the temporary substrate pads. The solder bumps are placed adjacent the corresponding sacrificial metal layer and heated to form an electrical and mechanical connection between the chip and the temporary substrate. The chip is then tested and/or burned-in on the temporary substrate. After testing/burn-in, the sacrificial metal layer is dissolved into the solder bumps by heating. The integrated circuit chip, including a solder bump having the dissolved sacrificial metal layer therein, may be easily removed from the temporary substrate. Solder bumps may also be formed on the temporary substrate and transferred to unbumped chips. Solder bumps with different characteristics may be formed by varying the current-time product to each individual pad of the temporary substrate during a plating operation.
Inventors
- 👤 Nicholas G. Koopman
- 👤 Glenn A. Rinne
- 👤 Iwona Turlik
- 👤 Edward K. Yung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:29
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/286; G01R31/2863; H; H10; H10P; H10P74/00; H10P74/27; H10P74/273; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/63; H10W70/65; H10W70/654; H10W70/655; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W72/29; H10W72/90; H10W72/941; H10W72/9415; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
151 words
A method of testing an integrated circuit chip having a plurality of input/output pads on one face thereof, comprising the steps of: providing a temporary substrate, having a plurality of temporary substrate pads at one face thereof, at locations corresponding to input/output pads on an integrated circuit chip; forming a sacrificial conductor layer on said temporary substrate pads; placing an integrated circuit chip adjacent said temporary substrate, with the input/output pads thereof adjacent said sacrificial conductor layer, and a solder bump between a respective input/output pad and said sacrificial conductor layer; heating said solder bumps to form a solid phase mechanical and electrical connection between corresponding input/output pads and temporary substrate pads; testing said integrated circuit chip on said temporary substrate; dissolving said sacrificial conductor layer into said solder bumps; and removing said integrated circuit chip, including said solder bumps having the dissolved sacrificial conductor layer therein, from said temporary substrate.
Claim 2
Independent Claim
151 words
A method of testing an integrated circuit chip having a plurality of input/output pads on one face thereof, comprising the steps of: providing a temporary substrate, having a plurality of temporary substrate pads at one face thereof, at locations corresponding to input/output pads on an integrated circuit chip; forming a sacrificial conductor layer on said temporary substrate pads; placing an integrated circuit chip adjacent said temporary substrate, with the input/output pads thereof adjacent said sacrificial conductor layer, and a solder bump between a respective input/output pad and said sacrificial conductor layer; heating said solder bumps to form a solid phase mechanical and electrical connection between corresponding input/output pads and temporary substrate pads; testing said integrated circuit chip on said temporary substrate; dissolving said sacrificial conductor layer into said solder bumps; and removing said integrated circuit chip, including said solder bumps having the dissolved sacrificial conductor layer therein, from said temporary substrate.
Claim 3
Dependent Claim
27 words
The method of claim 1 wherein said placing step is preceded by the step of: forming a solder bump on a respective integrated circuit chip input/output pad.
Claim 4
Dependent Claim
33 words
The method of claim 1 wherein the following step is performed between said forming and said placing steps: forming a solder bump on the sacrificial conductor layer on a respective temporary substrate pad.
Claim 5
Dependent Claim
43 words
The method of claim 3 wherein said solder bump forming step comprises the step of plating a solder bump on the sacrificial conductor layer on a respective temporary substrate pad, such that at least two of said solder bumps are of different size.
Claim 6
Dependent Claim
52 words
The method of claim 1 wherein said solder bumps comprise a material which is non-wettable to said temporary substrate pad and wherein said sacrificial conductor layer comprises a material which is dissolvable into said solder bumps and which is wettable to said solder bumps and is adherent to said temporary substrate pads.
Claim 7
Dependent Claim
21 words
The method of claim 5 wherein said solder bumps comprise lead-tin solder and said sacrificial conductor layer comprises a copper layer.
Claim 8
Dependent Claim
36 words
The method of claim 1 wherein said removing step is followed by the step of: mounting said integrated circuit chip, including said solder bumps having the dissolved sacrificial metal layer therein, on a next level package.
Claim 9
Dependent Claim
37 words
The method of claim 1 wherein said testing step comprises at least one of the steps of performing parametric measurements on, performing functional measurements on, programming, erasing, or burning-in said integrated circuit chip on said temporary substrate.
Claim 10
Dependent Claim
24 words
The method of claim 1 wherein said dissolving step comprises the step of dissolving said sacrificial conductor layer into said solder bumps by heating.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-28 | 1997-08-30 | 1998-03-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-28 | 2001-08-30 | 2002-03-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-28 | 2005-08-30 | 2006-03-01 | $7700.00 | Window Closed / Lapsed |