US5159752A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Scanning electron microscope based parametric testing method and apparatus
Assignee: Texas Instruments Inc
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Filing: 1990-11-30
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Granted: 1992-11-03
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Expires: 2010-11-30
Abstract
Abstract A scanning electron microscope (28) is connected to a test structure (48) formed on a semiconductor wafer. The test structure (48) comprises a plurality of first parallel structures (54) and a plurality of second parallel structure (56) transverse to and interlocking with the first structures (54). An island (60) is formed within a grid (58) formed by the structures (54-56) and is separated therefrom. An electron beam (38) from the scanning electron microscope (28) is aimed at the structure (48) and secondary electrons emitted therefrom are visually displayed on a monitor (44). The visual display (47) provides information on whether the island (60) is electrically separated from the mesh (58) or shorted thereto by comparing the intensity of the various islands (60).
Inventors
- 👤 Shivaling S. Mahant-Shetti
- 👤 Thomas J. Aton
- 👤 Rebecca J. Gale
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 01:57
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/302; G01R31/305; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
83 words
A method for evaluating and testing manufacturing processes on a semiconductor wafer, comprising the steps of: providing a test structure having a first conductive region and a second conductive region; biasing said first conductive region; directing an irradiating beam at said second conductive region to free electrons from said test structure, wherein said free electrons represent the conductivity or isolation between said first and second conductive regions; and detecting a portion of said free electrons to allow evaluation and testing of the processes.
Claim 2
Independent Claim
83 words
A method for evaluating and testing manufacturing processes on a semiconductor wafer, comprising the steps of: providing a test structure having a first conductive region and a second conductive region; biasing said first conductive region; directing an irradiating beam at said second conductive region to free electrons from said test structure, wherein said free electrons represent the conductivity or isolation between said first and second conductive regions; and detecting a portion of said free electrons to allow evaluation and testing of the processes.
Claim 3
Dependent Claim
18 words
The method of claim 1, wherein said test structure is formed separately from the integrated circuits being fabricated.
Claim 4
Dependent Claim
14 words
The method of claim 1, wherein said test structure comprises integrated circuitry being fabricated.
Claim 5
Dependent Claim
27 words
The method of claim 1, wherein said test structure is formed on a first wafer separate from a second wafer which includes the integrated circuitry being fabricated.
Claim 6
Dependent Claim
35 words
The method of claim 1, wherein a plurality of second conductive regions are formed by locating said second conductive regions progressively closer to said first region in a predetermined sequence to locate a failure spacing.
Claim 7
Dependent Claim
15 words
The method of claim 1, wherein no connection is made to said second conductive region.
Claim 8
Independent Claim
78 words
A method for checking defect density of integrated circuitry being fabricated on a semiconductor wafer, comprising the steps of: forming a test structure having a first conductive region and a second conductive region on the wafer; biasing said first conductive region at a common potential; aiming at least one irradiating beam at said second conductive region to free electrons from said test structure; displaying a depiction of said free electrons to allow evaluation and testing of the processes.
Claim 9
Independent Claim
78 words
A method for checking defect density of integrated circuitry being fabricated on a semiconductor wafer, comprising the steps of: forming a test structure having a first conductive region and a second conductive region on the wafer; biasing said first conductive region at a common potential; aiming at least one irradiating beam at said second conductive region to free electrons from said test structure; displaying a depiction of said free electrons to allow evaluation and testing of the processes.
Claim 10
Dependent Claim
19 words
The method of claim 7, wherein said test structure comprises circuitry formed separately from said integrated circuitry being fabricated.
Claim 11
Dependent Claim
35 words
The method of claim 8, wherein a plurality of second conductive regions are formed by locating said second conductive regions progressively closer to said first region in a predetermined sequence to locate a failure spacing.
Claim 12
Dependent Claim
15 words
The method of claim 7, wherein said test structure comprises said integrated circuitry being fabricated.
Claim 13
Dependent Claim
17 words
The method of claim 7, wherein the step of displaying comprises displaying connectivity of said test structure.
Claim 14
Dependent Claim
17 words
The method of claim 7, wherein the step of displaying comprises displaying isolation of said test structure.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-03 | 1996-05-04 | 1996-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-03 | 2000-05-04 | 2000-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-03 | 2004-05-04 | 2004-11-03 | $7700.00 | Window Closed / Lapsed |