US6991970B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of semiconductor device
Assignee: Micron Technology Inc
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Filing: 2001-08-30
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Granted: 2006-01-31
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Expires: 2021-08-30
Abstract
Abstract A method used to form a semiconductor device comprises providing first and second circuit portions having first and second pad portions respectively. The second circuit portion is electrically isolated from the first circuit portion. The first and second pad portions are then electrically connected, for example with a ball bond or a wire bond, to electrically couple the first and second circuit portions. In various embodiments the semiconductor device will not function until the pad portions are electrically coupled, and in other embodiments the functionality of the device may be selectively controlled by connecting selected pad portions from a plurality of pad portions. Isolating the first and second circuit portions allows electrical operations such as antifuse programming to be carried out without adversely affecting related circuits. Once electrical operations are completed, the isolated circuit portions are electrically coupled to provide a complete circuit. Various inventive embodiments and implementations are described.
Inventors
- 👤 Rich Fogal
- 👤 Tracy Reynolds
- 👤 Timothy Cowles
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:07
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; G11C29/00; G11C29/02; G11C29/028; G11C29/70; G11C29/88; G11C29/883; H10P; H10P74/00; H10P74/27; H10P74/273; H10W20/01; H10W20/031; H10W20/067; H10W72/00; H10W72/90; H10W72/071; H10W72/072; H10W72/07251; H10W72/07254; H10W72/20; H10W72/241; H10W72/242; H10W72/244; H10W72/921; H10W72/923; H10W72/931; H10W72/932
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
156 words
A method of manufacturing a semiconductor device, comprising: forming a first circuit and a second circuit on a semiconductor wafer substrate assembly; forming a first conductor connected to the first semiconductor circuit and a second conductor connected to the second semiconductor circuit, wherein the first conductor is electrically separated from the second conductor such that the first and second circuits are sufficiently isolated to provide protection to the second circuit; with the first and second circuits electrically separate from each other, performing an electrical operation on the first circuit with a voltage sufficient to damage the second circuit when applied to the first circuit with the first and second circuits electrically connected to each other; subsequent to performing the electrical operation on the first circuit, shorting the first and second conductors together to electrically couple the first and second circuits; and subsequent to shorting the first and second conductors together, encapsulating the semiconductor wafer substrate assembly.
Claim 2
Independent Claim
156 words
A method of manufacturing a semiconductor device, comprising: forming a first circuit and a second circuit on a semiconductor wafer substrate assembly; forming a first conductor connected to the first semiconductor circuit and a second conductor connected to the second semiconductor circuit, wherein the first conductor is electrically separated from the second conductor such that the first and second circuits are sufficiently isolated to provide protection to the second circuit; with the first and second circuits electrically separate from each other, performing an electrical operation on the first circuit with a voltage sufficient to damage the second circuit when applied to the first circuit with the first and second circuits electrically connected to each other; subsequent to performing the electrical operation on the first circuit, shorting the first and second conductors together to electrically couple the first and second circuits; and subsequent to shorting the first and second conductors together, encapsulating the semiconductor wafer substrate assembly.
Claim 3
Dependent Claim
18 words
The method of claim 1 further comprising shorting the first and second conductors together with a ball bond.
Claim 4
Dependent Claim
33 words
The method of claim 1 wherein the first and second circuits are fabricated such that the semiconductor device is inoperative if when the first and second conductors remain electrically separate subsequent to encapsulation.
Claim 5
Dependent Claim
31 words
The method of claim 1 further comprising: providing a lead frame; and subsequent to shorting the first and second conductors together, attaching the semiconductor wafer substrate assembly to the lead frame.
Claim 6
Independent Claim
136 words
A method of manufacturing a memory device, comprising: forming a plurality of primary and redundant memory cell locations; forming antifuse circuitry which allows selection of the redundant memory cell locations; forming voltage sensitive circuitry on the semiconductor wafer substrate assembly; forming a first conductor electrically connected with the antifuse circuitry; forming a second conductor electrically connected with the voltage sensitive circuitry, wherein the first and second conductors are electrically separated from each other; while the first and second conductors are electrically separated, applying a voltage to the antifuse circuitry to program the antifuse circuitry, wherein the voltage is sufficient to damage the voltage sensitive circuitry when applied to the antifuse circuitry when the first and second conductors are electrically connected; and subsequent to programming the antifuse circuitry, electrically shorting the first conductor with the second conductor.
Claim 7
Independent Claim
136 words
A method of manufacturing a memory device, comprising: forming a plurality of primary and redundant memory cell locations; forming antifuse circuitry which allows selection of the redundant memory cell locations; forming voltage sensitive circuitry on the semiconductor wafer substrate assembly; forming a first conductor electrically connected with the antifuse circuitry; forming a second conductor electrically connected with the voltage sensitive circuitry, wherein the first and second conductors are electrically separated from each other; while the first and second conductors are electrically separated, applying a voltage to the antifuse circuitry to program the antifuse circuitry, wherein the voltage is sufficient to damage the voltage sensitive circuitry when applied to the antifuse circuitry when the first and second conductors are electrically connected; and subsequent to programming the antifuse circuitry, electrically shorting the first conductor with the second conductor.
Claim 8
Dependent Claim
33 words
The method of claim 5 further comprising encapsulating the antifuse circuitry, the voltage sensitive circuitry, the first conductor, and the second conductor subsequent to electrically shorting the first conductor with the second conductor.
Claim 9
Dependent Claim
20 words
The method of claim 5 further comprising electrically shorting the first conductor with the second conductor using a ball bond.
Claim 10
Dependent Claim
32 words
The method of claim 5 wherein the antifuse circuitry and the voltage sensitive circuitry are fabricated such that the memory device is inoperative if the first and second conductors remain electrically separated.
Claim 11
Dependent Claim
28 words
The method of claim 5 further comprising: providing a lead frame; and subsequent to bridging the physical opening, attaching the semiconductor wafer substrate assembly to the lead frame.
Claim 12
Independent Claim
134 words
A method of manufacturing a memory device comprising: fabricating first and second circuits on a semiconductor wafer substrate assembly, wherein the first and second circuits are adapted to be electrically connected through a common conductor; fabricating the common conductor with a physical opening to provide an open circuit between the first and second circuits, such that the first circuit is sufficiently isolated from the second circuit to provide protection for the first circuit from a voltage applied to the second circuit which is sufficient to damage the first circuit when applied to the second circuit with the physical opening bridged; applying the voltage to the second circuit; and subsequent to applying the voltage to the second circuit, bridging the physical opening of the common conductor to electrically connect the first and second circuits together.
Claim 13
Independent Claim
134 words
A method of manufacturing a memory device comprising: fabricating first and second circuits on a semiconductor wafer substrate assembly, wherein the first and second circuits are adapted to be electrically connected through a common conductor; fabricating the common conductor with a physical opening to provide an open circuit between the first and second circuits, such that the first circuit is sufficiently isolated from the second circuit to provide protection for the first circuit from a voltage applied to the second circuit which is sufficient to damage the first circuit when applied to the second circuit with the physical opening bridged; applying the voltage to the second circuit; and subsequent to applying the voltage to the second circuit, bridging the physical opening of the common conductor to electrically connect the first and second circuits together.
Claim 14
Dependent Claim
23 words
The method of claim 10 further comprising encapsulating the first and second circuits and the common conductor subsequent to bridging the physical opening.
Claim 15
Dependent Claim
15 words
The method of claim 10 further comprising bridging the physical opening with a ball bond.
Claim 16
Dependent Claim
26 words
The method of claim 10 wherein the first and second circuits are fabricated such that the memory device is inoperative if the physical opening remains unbridged.
Claim 17
Dependent Claim
28 words
The method of claim 10 further comprising: providing a lead frame; and subsequent to bridging the physical opening, attaching the semiconductor wafer substrate assembly to the lead frame.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-01-30 | 2009-08-01 | 2010-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-01-30 | 2013-08-01 | 2014-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-01-30 | 2017-08-01 | 2018-01-31 | $7700.00 | Window Closed / Lapsed |