US6169329B1 — Semiconductor devices having interconnections usi…

Claim 1

Independent Claim 280 words

A semiconductor device, comprising: a carrier substrate including a plurality of conductors on a surface thereof, the conductors of the plurality being arranged to mate with an array of external connections of a pitch and pattern and located over and projecting from an active surface of a first die; a second die having an active surface with a plurality of bond pads arranged thereover in an arrangement at least partially different from the arrangement of the plurality of conductors on the surface of the carrier substrate; a plurality of external connections on the second die located over and projecting from an active surface thereof, at least some of the plurality of external connections on the secind die being offset from at least some of the plurality of bond pads thereof, said plurality of external connections arranged in an array over the active surface of the second die, the array of external connections of the second die being arranged to substantially correspond in pitch and pattern to the pitch and pattern of the external connections of the array located over the active surface of the first die, the plurality of external connections of the second die being in mating contact with the conductors of the plurality on the surface of the carrier substrate; and a plurality of circuit traces extending over the active surface of the second die and connecting at least some of the plurality of external connections on the second die to at least some of the plurality of bond pads on the second die; wherein the second die differs from the first die in at least one of the following respects: size, shape, bond pad arrangement and circuitry.

Claim 2

Dependent Claim 280 words

A semiconductor device, comprising: a carrier substrate including a plurality of conductors on a surface thereof, the conductors of the plurality being arranged to mate with an array of external connections of a pitch and pattern and located over and projecting from an active surface of a first die; a second die having an active surface with a plurality of bond pads arranged thereover in an arrangement at least partially different from the arrangement of the plurality of conductors on the surface of the carrier substrate; a plurality of external connections on the second die located over and projecting from an active surface thereof, at least some of the plurality of external connections on the secind die being offset from at least some of the plurality of bond pads thereof, said plurality of external connections arranged in an array over the active surface of the second die, the array of external connections of the second die being arranged to substantially correspond in pitch and pattern to the pitch and pattern of the external connections of the array located over the active surface of the first die, the plurality of external connections of the second die being in mating contact with the conductors of the plurality on the surface of the carrier substrate; and a plurality of circuit traces extending over the active surface of the second die and connecting at least some of the plurality of external connections on the second die to at least some of the plurality of bond pads on the second die; wherein the second die differs from the first die in at least one of the following respects: size, shape, bond pad arrangement and circuitry.

Claim 3

Dependent Claim 40 words

The semiconductor device of claim 1 , wherein at least a portion of at least one of said plurality of circuit traces is disposed on a discrete layer of dielectric material residing on said active surface of said second die.

Claim 4

Dependent Claim 26 words

The semiconductor device of claim 2 , wherein said dielectric material is selected from the group comprising a polyimide, a siloxane polyimide and a spin-on glass.

Claim 5

Dependent Claim 28 words

The semiconductor device of claim 1 , wherein at least a portion of at least one of said plurality of circuit traces is covered by a dielectric material.

Claim 6

Dependent Claim 26 words

The semiconductor device of claim 4 , wherein said dielectric material is selected from the group comprising a polyimide, a siloxane polyimide and a spin-on glass.

Claim 7

Dependent Claim 25 words

The semiconductor device of claim 1 , wherein said external connection arrays of said first die and said second die comprise arrays of conductive bumps.

Claim 8

Dependent Claim 32 words

The semiconductor device of claim 6 , wherein said bumps are of a material selected from the group comprising a reflowable metal material, a conductive polymer and a polymer carrying conductive material.

Claim 9

Dependent Claim 24 words

The semiconductor device of claim 6 , wherein said external connection arrays of said first die and said second die each comprise a BGA.

Claim 10

Dependent Claim 26 words

The semiconductor device of claim 1 , wherein said second die is reduced in size in at least one dimension in comparison to said first die.

Claim 11

Dependent Claim 18 words

The semiconductor device of claim 9 , wherein said second die is a shrink of said first die.

Claim 12

Dependent Claim 34 words

The semiconductor device of claim 1 , wherein said external arrays of connections of said arrays of said first die and said second die are arranged in a single row on a center line.

Claim 13

Dependent Claim 29 words

The semiconductor device of claim 1 , wherein said external connections of said arrays of said first die and said second die are arranged in at least two rows.

Claim 14

Dependent Claim 35 words

The semiconductor device of claim 1 , wherein said external connections of said arrays of said first die and said second die are arranged in a rectangular configuration comprising at least one rectangle of connections.

Claim 15

Dependent Claim 28 words

The semiconductor device of claim 1 , wherein said external connections of said arrays of said first die and said second die are arranged in rows and columns.

Claim 16

Dependent Claim 33 words

The semiconductor device of claim 1 , wherein said external connection array of each of said first die and said second die comprises a circular array including at least one circle of connections.

Claim 17

Dependent Claim 175 words

A process of manufacturing a semiconductor device, comprising: fabricating a die having an active surface with a plurality of bond pads arranged on said die and over said active surface, wherein said fabricating said die includes shrinking another die which is larger in at least one external dimension than said die, said another die carrying an external connection array projecting from an active surface thereof; extending a plurality of circuit traces on said die and over said active surface of said die from at least some of said bond pads of said plurality to remote locations over said active surface and offset from said at least some of said bond pads of said plurality; and forming external connections projecting from said active surface of said die, at least some of said external connections of said die being disposed at said remote locations whereby said external connections of said die define an array of external connections of the same pattern and pitch as said external connection array projecting from said active surface of said another die.

Claim 18

Dependent Claim 175 words

A process of manufacturing a semiconductor device, comprising: fabricating a die having an active surface with a plurality of bond pads arranged on said die and over said active surface, wherein said fabricating said die includes shrinking another die which is larger in at least one external dimension than said die, said another die carrying an external connection array projecting from an active surface thereof; extending a plurality of circuit traces on said die and over said active surface of said die from at least some of said bond pads of said plurality to remote locations over said active surface and offset from said at least some of said bond pads of said plurality; and forming external connections projecting from said active surface of said die, at least some of said external connections of said die being disposed at said remote locations whereby said external connections of said die define an array of external connections of the same pattern and pitch as said external connection array projecting from said active surface of said another die.

Claim 19

Dependent Claim 29 words

The process of claim 16 , further including covering at least a portion of at least one of said plurality of circuit traces with a layer of dielectric material.

Claim 20

Dependent Claim 34 words

The process of claim 16 , further including forming at least a portion of at least one of said plurality of circuit traces over a layer of dielectric material applied to said active surface.

Claim 21

Dependent Claim 15 words

The process of claim 16 , further including forming said external connections as conductive bumps.

Claim 22

Dependent Claim 31 words

The process of claim 19 , wherein said external connections are formed of a material selected from the group comprising a metal, a conductive polymer, and a polymer carrying conductive material.

Claim 23

Dependent Claim 46 words

The process of claim 16 , further including providing a substrate bearing conductors thereon having contact areas in a pattern matching said external connection array and connecting said die by said external connections of said array to at least some of said substrate conductor contact areas.

Claim 24

Independent Claim 176 words

A method of designing a die-adaptable semiconductor device assembly, comprising: identifying at least one integrated circuit function to be fabricated on an active surface of a semiconductor die; identifying a number of external connections for electrically communicating said at least one integrated circuit function to external circuitry; selecting an external connection array of a given configuration and pitch of connections for effecting said electrical communication between said active surface of a semiconductor die including said at least one integrated circuit function and said external circuitry; and positioning a different, selected external connection array having said given configuration and pitch of connections on the active surface of each of at least two semiconductor dies to enable said electrical communication by each of said at least two semiconductor dies directly to said external circuitry through said external connection array, said at least two semiconductor dies differing in at least one of the following respects: size, shape, and bond pad arrangement, and each of said at least two semiconductor dies including said at least one identified integrated circuit function.

Claim 25

Independent Claim 176 words

A method of designing a die-adaptable semiconductor device assembly, comprising: identifying at least one integrated circuit function to be fabricated on an active surface of a semiconductor die; identifying a number of external connections for electrically communicating said at least one integrated circuit function to external circuitry; selecting an external connection array of a given configuration and pitch of connections for effecting said electrical communication between said active surface of a semiconductor die including said at least one integrated circuit function and said external circuitry; and positioning a different, selected external connection array having said given configuration and pitch of connections on the active surface of each of at least two semiconductor dies to enable said electrical communication by each of said at least two semiconductor dies directly to said external circuitry through said external connection array, said at least two semiconductor dies differing in at least one of the following respects: size, shape, and bond pad arrangement, and each of said at least two semiconductor dies including said at least one identified integrated circuit function.

Claim 26

Dependent Claim 34 words

The method of claim 22 , further comprising providing said at least two semiconductor dies in the form of a first die and a second die which comprises a shrink of said first die.

Claim 27

Dependent Claim 27 words

The method of claim 22 , further comprising providing said at least two semiconductor dies in the form of first and second dies of different manufacturing origin.

Claim 28

Dependent Claim 57 words

The method of claim 22 , further including configuring circuit traces on at least one of said at least two semiconductor dies extending between locations of said external connections of said external connection array on said at least one semiconductor die and at least some bond pad locations on the active surface of the same semiconductor die.

Claim 29

Dependent Claim 54 words

The method of claim 25 , wherein said at least some bond pad locations are located peripherally on said active surface of said at least one of said at least two semiconductor dies, and further comprising locating said external connection array relatively centrally on said active surfaces of said at least two semiconductor dies.

Claim 30

Dependent Claim 85 words

The method of claim 22 , further comprising providing said at least two semiconductor dies in the form of at least a first die and at least one shrink of said first die, and further including selecting a pattern of circuit traces whereby at least some of said circuit traces extend from at least some bond pad locations on said first die to at least some of said external connections and pass through at least some bond pad locations of said at least one shrink.

Claim 31

Dependent Claim 178 words

The method of claim 22 , further comprising designing an external connection array adapter usable with at least one of said at least two semiconductor dies and carrying said selected external connection array thereon, said at least one of said at least two semiconductor dies including bond pads offset from locations of said selected external connection array, configuring said external connection array adapter for disposition on the active surface of said at least one of said at least two semiconductor dies and including circuit traces communicating between bond pad locations of said at least one of said at least two semiconductor dies and external connections of said selected external connection array on said external connection array adapter, said positioning of said external connection array on said at least one of said at least two semiconductor dies comprising applying said external connection array adapter to the active surface thereof with at least some bond pads of said at least one of said at least two semiconductor die in communication with at least some of said different, selected circuit traces.

Claim 32

Dependent Claim 234 words

A semiconductor device, comprising: a plurality of external connections arranged in an array selected for disposition over, and to project from, an active surface of each of a first die and a second die, the second die differing from the first die in at least one of the following respects: size, shape, bond pad arrangement and circuitry, wherein the array of external connections is of a pitch and pattern suitable for mating with conductors carried on a surface of a substrate; wherein each die of the first die and the second die carries external connections arranged in the array on an active surface thereof, at least one die of the first die and the second die includes a plurality of bond pads over an active surface thereof including integrated circuitry, at least some of the plurality of bond pads are located on the at least one die laterally offset from at least some external connection locations of the array carried thereon and a plurality of circuit traces extend over the active surface of the at least one die and connect the at least some of the plurality of bond pads on the at least one die to the at least some external connections of the array carried on the at least one die from which the at least some of the plurality of bond pads of the at least one die are laterally offset.

Claim 33

Dependent Claim 234 words

A semiconductor device, comprising: a plurality of external connections arranged in an array selected for disposition over, and to project from, an active surface of each of a first die and a second die, the second die differing from the first die in at least one of the following respects: size, shape, bond pad arrangement and circuitry, wherein the array of external connections is of a pitch and pattern suitable for mating with conductors carried on a surface of a substrate; wherein each die of the first die and the second die carries external connections arranged in the array on an active surface thereof, at least one die of the first die and the second die includes a plurality of bond pads over an active surface thereof including integrated circuitry, at least some of the plurality of bond pads are located on the at least one die laterally offset from at least some external connection locations of the array carried thereon and a plurality of circuit traces extend over the active surface of the at least one die and connect the at least some of the plurality of bond pads on the at least one die to the at least some external connections of the array carried on the at least one die from which the at least some of the plurality of bond pads of the at least one die are laterally offset.

Claim 34

Dependent Claim 21 words

The semiconductor device of claim 29 , wherein the plurality of circuit traces is formed on the at least one die.

Claim 35

Dependent Claim 30 words

The semiconductor device of claim 29 , wherein the plurality of circuit traces is preformed on a dielectric carrier applied to said active surface of the at least one die.

Claim 36

Dependent Claim 21 words

The semiconductor device of claim 29 , wherein the plurality of traces is at least partially covered by a dielectric material.

Claim 37

Dependent Claim 14 words

The semiconductor device of claim 29 , wherein the external connections comprise conductive bumps.

Claim 38

Independent Claim 101 words

A method of reconfiguring die I/O patterns, comprising: selecting a first die having an active surface bearing a first I/O pattern on an active surface thereof; selecting a second die having an active surface bearing a second I/O pattern on an active surface thereof, said second I/O pattern being different from said first I/O pattern; and reconfiguring at least one of said first and said second active surface I/O patterns on an active surface of at least one of said respective dies so that said first die and said second die present a common I/O pattern from their respective active surfaces.

Claim 39

Independent Claim 101 words

A method of reconfiguring die I/O patterns, comprising: selecting a first die having an active surface bearing a first I/O pattern on an active surface thereof; selecting a second die having an active surface bearing a second I/O pattern on an active surface thereof, said second I/O pattern being different from said first I/O pattern; and reconfiguring at least one of said first and said second active surface I/O patterns on an active surface of at least one of said respective dies so that said first die and said second die present a common I/O pattern from their respective active surfaces.

Claim 40

Dependent Claim 41 words

The method of claim 34 , wherein said common I/O pattern differs from both said first I/O pattern and said second I/O pattern, and further comprising reconfiguring both of said first and second I/O patterns to present said common I/O pattern.

Claim 41

Dependent Claim 51 words

The semiconductor device of claim 12 , wherein an arrangement of said at least two rows is selected from an arrangement wherein said at least two rows are mutually parallel and an arrangement wherein said at least two rows include a first row and a second row which are mutually perpendicular.

Claim 42

Dependent Claim 26 words

The semiconductor device of claim 14 , wherein said external connections of a row are offset from said external connections of at least one adjacent row.

Claim 43

Dependent Claim 158 words

A process of manufacturing a semiconductor device, comprising: fabricating a die having an active surface with a plurality of bond pads arranged on said die and over said active surface, said die differing from another selected die in at least one of the following respects: size, shape, bond pad arrangement and circuitry, said another selected die carrying an external connection array thereon; extending a plurality of circuit traces on said die and over said active surface thereof from at least some of said bond pads to locations over said active surface remote therefrom and laterally offset from said at least some bond pads; and forming external connections projecting from said active surface of said die at locations including said locations remote from said at least some of said bond pads to define an array of external connections of the same pattern and pitch as a pattern and pitch of said external connection array of said another selected die.

Claim 44

Dependent Claim 158 words

A process of manufacturing a semiconductor device, comprising: fabricating a die having an active surface with a plurality of bond pads arranged on said die and over said active surface, said die differing from another selected die in at least one of the following respects: size, shape, bond pad arrangement and circuitry, said another selected die carrying an external connection array thereon; extending a plurality of circuit traces on said die and over said active surface thereof from at least some of said bond pads to locations over said active surface remote therefrom and laterally offset from said at least some bond pads; and forming external connections projecting from said active surface of said die at locations including said locations remote from said at least some of said bond pads to define an array of external connections of the same pattern and pitch as a pattern and pitch of said external connection array of said another selected die.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2004-01-02	2004-07-03	2005-01-02	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2008-01-02	2008-07-03	2009-01-02	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2012-01-02	2012-07-03	2013-01-02	$7700.00	Window Closed / Lapsed

Semiconductor devices having interconnections using standardized bonding locations and methods of designing

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