US5490324A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making integrated circuit package having multiple bonding tiers
Assignee: LSI Corp
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Filing: 1993-09-15
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Granted: 1996-02-13
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Expires: 2013-09-15
Abstract
Abstract An integrated circuit package, as well as a method for fabricating the same, is herein disclosed. The integrated circuit package of the present invention includes a cavity located within an assembly of laminated printed wiring boards. Such cavity provides two or more bonding tiers for connection with a semiconductor die. The contact pads are further connected, through conductive vias, to external connection means such as solder balls or pins. The semiconductor die is encapsulated with a molding compound through a transfer molding process. The present invention is especially advantageous in manufacturing pin grid array ("PGA") and ball grid array ("BGA")integrated circuit packages.
Inventors
- 👤 Keith G. Newman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:33
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/685; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W74/117; H10W90/00; H10W90/701; H10W70/682; H10W72/00; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W72/541; H10W72/5449; H10W72/547; H10W72/5473; H10W90/751; H10W90/754; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49126
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
210 words
A method for fabricating an integrated circuit package, comprising: (a) laminating printed wiring boards to one another, some of the printed wiring boards having consecutively larger openings so as to form a cavity having two or more bonding tiers, the two or more bonding tiers having contact pads disposed thereon; (b) placing a semiconductor die in the cavity, the semiconductor die including bond pads thereon; (c) connecting the bond pads of the semiconductor die to the contact pads; (d) attaching external connection means to one or more of the laminated printed wiring boards; (e) connecting the contact pads to the external connection means; (f) placing the semiconductor die and laminated printed wiring boards within a particular one of a plurality of molding cavities, each of the plurality of molding cavities being connected to a central container by a plurality of respective paths; (g) placing molding compound within the central container; (h) heating and pressurizing the central cavity so as to force the molding compound to flow from the central container, through the plurality of respective paths, and into the particular molding cavity; and (i) permitting the molding compound to harden within the particular molding cavity so as to encapsulate the semiconductor die and laminated printed wiring boards with molding compound.
Claim 2
Independent Claim
210 words
A method for fabricating an integrated circuit package, comprising: (a) laminating printed wiring boards to one another, some of the printed wiring boards having consecutively larger openings so as to form a cavity having two or more bonding tiers, the two or more bonding tiers having contact pads disposed thereon; (b) placing a semiconductor die in the cavity, the semiconductor die including bond pads thereon; (c) connecting the bond pads of the semiconductor die to the contact pads; (d) attaching external connection means to one or more of the laminated printed wiring boards; (e) connecting the contact pads to the external connection means; (f) placing the semiconductor die and laminated printed wiring boards within a particular one of a plurality of molding cavities, each of the plurality of molding cavities being connected to a central container by a plurality of respective paths; (g) placing molding compound within the central container; (h) heating and pressurizing the central cavity so as to force the molding compound to flow from the central container, through the plurality of respective paths, and into the particular molding cavity; and (i) permitting the molding compound to harden within the particular molding cavity so as to encapsulate the semiconductor die and laminated printed wiring boards with molding compound.
Claim 3
Dependent Claim
22 words
The method as recited in claim 1, comprising the further step of constricting the molding compound from entering the particular molding cavity.
Claim 4
Independent Claim
131 words
A method for fabricating an integrated circuit package, comprising: (a) laminating printed wiring boards to one another, some of the printed wiring boards having consecutively larger openings so as to form a cavity having two or more bonding tiers, the two or more bonding tiers having contact pads disposed thereon; (b) placing a semiconductor die in the cavity, the semiconductor die including bond pads thereon; (c) connecting the bond pads of the semiconductor die to the contact pads; (d) attaching external connection means to one or more of the laminated printed wiring boards; (e) connecting the contact pads to the external connection means by plating vias through the laminated printed wiring boards; and (f) encapsulating the semiconductor die and laminated printed wiring boards with molding compound by a transfer molding process.
Claim 5
Independent Claim
131 words
A method for fabricating an integrated circuit package, comprising: (a) laminating printed wiring boards to one another, some of the printed wiring boards having consecutively larger openings so as to form a cavity having two or more bonding tiers, the two or more bonding tiers having contact pads disposed thereon; (b) placing a semiconductor die in the cavity, the semiconductor die including bond pads thereon; (c) connecting the bond pads of the semiconductor die to the contact pads; (d) attaching external connection means to one or more of the laminated printed wiring boards; (e) connecting the contact pads to the external connection means by plating vias through the laminated printed wiring boards; and (f) encapsulating the semiconductor die and laminated printed wiring boards with molding compound by a transfer molding process.
Claim 6
Dependent Claim
42 words
The method as recited in claim 3, wherein encapsulating the semiconductor die and laminated printed wiring boards with molding compound by a transfer molding process, includes applying thermosetting polymers to the semiconductor die and laminated printed wiring boards through a constricted passage.
Claim 7
Dependent Claim
18 words
The method as recited in claim 3, wherein the external connection means are an array of metal pins.
Claim 8
Dependent Claim
18 words
The method as recited in claim 3, wherein the external connection means are an array of solder balls.
Claim 9
Dependent Claim
26 words
The method as recited in claim 3, wherein the contact pads are arranged in a rectangular array on each of the two or more bonding tiers.
Claim 10
Dependent Claim
16 words
The method as recited in claim 3 wherein the printed wiring boards comprise completely cured epoxy.
Claim 11
Independent Claim
145 words
A method for fabricating an integrated circuit package, comprising: (a) providing a base printed wiring board; (b) laminating at least one printed wiring boards having consecutively larger centrally disposed openings to the base printed wiring board so that a centrally located cavity defined by consecutively larger bonding tiers is formed; (c) disposing contact pads in the cavity; (d) placing a semiconductor die in the cavity and above the base printed wiring board, the semiconductor die having bond pads disposed thereon; (e) connecting the bond pads of the semiconductor die to the contact pads through bond wires; (f) encapsulating the cavity, including the semiconductor die, the connections between the bond pads and contact pads and a portion of the at least one printed wiring boards but not the periphery of the at least one printed wiring boards, with a molding compound by a transfer molding process.
Claim 12
Independent Claim
145 words
A method for fabricating an integrated circuit package, comprising: (a) providing a base printed wiring board; (b) laminating at least one printed wiring boards having consecutively larger centrally disposed openings to the base printed wiring board so that a centrally located cavity defined by consecutively larger bonding tiers is formed; (c) disposing contact pads in the cavity; (d) placing a semiconductor die in the cavity and above the base printed wiring board, the semiconductor die having bond pads disposed thereon; (e) connecting the bond pads of the semiconductor die to the contact pads through bond wires; (f) encapsulating the cavity, including the semiconductor die, the connections between the bond pads and contact pads and a portion of the at least one printed wiring boards but not the periphery of the at least one printed wiring boards, with a molding compound by a transfer molding process.
Claim 13
Dependent Claim
17 words
The method as recited in claim 9, wherein the bond wires are substantially parallel with one another.
Claim 14
Dependent Claim
22 words
The method as recited in claim 9, further comprising: plating vias through the periphery of the one or more printed wiring boards.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-12 | 1999-08-14 | 2000-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-12 | 2003-08-14 | 2004-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-12 | 2007-08-14 | 2008-02-13 | $7700.00 | Window Closed / Lapsed |