US5844304A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for manufacturing semiconductor device and semiconductor wafer
Assignee: NEC Electronics Corp
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Filing: 1995-09-25
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Granted: 1998-12-01
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Expires: 2015-09-25
Abstract
Abstract A process for manufacturing a semiconductor device includes defining chip sections on a wafer by scribe lines with each chip section having chip electrodes formed thereon. The wafer is covered with a passivating film except for on the chip electrodes. Aluminum interconnection layers are provided such that each layer is connected to the chip electrode at one end thereof and the other end of the layer is extended towards the central portion of the chip section. A cover coating film is applied on the passivating film and the layers. A number of apertures are formed in the coating film passing therethrough, and bump electrodes are formed at the position corresponding to the apertures. The chip sections are then separated from each other along the scribe lines into semiconductor devices.
Inventors
- 👤 Keiichiro Kata
- 👤 Shinichi Chikaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:41
CPC Classifications
H; H10; H10P; H10P54/00; H10W; H10W72/00; H10W72/01; H10W72/012; H10W70/00; H10W70/01; H10W70/05; H10W72/019; H10W72/071; H10W72/073; H10W72/20; H10W72/241; H10W72/244; H10W72/251; H10W72/252; H10W72/90; H10W72/921; H10W72/922; H10W72/923; H10W72/951; H10W72/952
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
102 words
A semiconductor wafer, including: a plurality of the sections defined thereon by scribe lines, each chip section having bump electrodes formed simultaneously thereon, the scribe lines for separating the chip sections from each other without dividing bump electrodes thereon, said chip section including: a plurality of chip electrodes positioned on said chip section; and a plurality of interconnection layers for electrically connecting said chip electrodes and said bump electrodes, said bump electrodes being located at positions other than over said chip electrodes, said chip section having a center and a periphery and said interconnection layers extend from said periphery toward said center.
Claim 2
Dependent Claim
102 words
A semiconductor wafer, including: a plurality of the sections defined thereon by scribe lines, each chip section having bump electrodes formed simultaneously thereon, the scribe lines for separating the chip sections from each other without dividing bump electrodes thereon, said chip section including: a plurality of chip electrodes positioned on said chip section; and a plurality of interconnection layers for electrically connecting said chip electrodes and said bump electrodes, said bump electrodes being located at positions other than over said chip electrodes, said chip section having a center and a periphery and said interconnection layers extend from said periphery toward said center.
Claim 3
Dependent Claim
82 words
A semiconductor wafer, including: a plurality of chip sections defined thereon by scribe lines, each chip section having: bump electrodes formed simultaneously thereon; a plurality of chip electrodes positioned on said chip section; and a plurality of interconnection layers for electrically connecting said chip electrodes and said bump electrodes, said bump electrodes being located at positions other than over said chip electrodes, said chip section having a center and a periphery and said interconnection layers extend from said periphery toward said center.
Claim 4
Dependent Claim
82 words
A semiconductor wafer, including: a plurality of chip sections defined thereon by scribe lines, each chip section having: bump electrodes formed simultaneously thereon; a plurality of chip electrodes positioned on said chip section; and a plurality of interconnection layers for electrically connecting said chip electrodes and said bump electrodes, said bump electrodes being located at positions other than over said chip electrodes, said chip section having a center and a periphery and said interconnection layers extend from said periphery toward said center.
Claim 5
Dependent Claim
118 words
A semiconductor wafer including: a plurality of chip sections defined thereon by scribe lines, each chip section having bump electrodes formed simultaneously thereon, the scribe lines for separating the chip sections from each other without dividing bump electrodes thereon, said chip section including: a plurality of chip electrodes positioned on said chip section; and a plurality of interconnection layers for electrically connecting said chip electrodes and said bump electrodes, said bump electrodes being located at positions other than over said chip electrodes, wherein each of said interconnection layers comprises an aluminum layer and a plating on said aluminum layer, wherein said plating contacts one of said bump electrodes and said aluminum layer contacts one of said chip electrodes.
Claim 6
Dependent Claim
118 words
A semiconductor wafer including: a plurality of chip sections defined thereon by scribe lines, each chip section having bump electrodes formed simultaneously thereon, the scribe lines for separating the chip sections from each other without dividing bump electrodes thereon, said chip section including: a plurality of chip electrodes positioned on said chip section; and a plurality of interconnection layers for electrically connecting said chip electrodes and said bump electrodes, said bump electrodes being located at positions other than over said chip electrodes, wherein each of said interconnection layers comprises an aluminum layer and a plating on said aluminum layer, wherein said plating contacts one of said bump electrodes and said aluminum layer contacts one of said chip electrodes.
Claim 7
Dependent Claim
93 words
A semiconductor wafer including: a plurality of chip sections defined thereon by scribe lines, each chip section having: bump electrodes formed simultaneously thereon; a plurality of chip electrodes positioned on said chip section; and a plurality of interconnection layers for electrically connecting said chip electrodes and said bump electrodes, said bump electrodes being located at positions other than over said chip electrodes, wherein each of said interconnection layers comprises an aluminum layer and a plating on said aluminum, wherein said plating contacts said bump electrode and said aluminum layer contacts said chip electrode.
Claim 8
Dependent Claim
93 words
A semiconductor wafer including: a plurality of chip sections defined thereon by scribe lines, each chip section having: bump electrodes formed simultaneously thereon; a plurality of chip electrodes positioned on said chip section; and a plurality of interconnection layers for electrically connecting said chip electrodes and said bump electrodes, said bump electrodes being located at positions other than over said chip electrodes, wherein each of said interconnection layers comprises an aluminum layer and a plating on said aluminum, wherein said plating contacts said bump electrode and said aluminum layer contacts said chip electrode.
Claim 9
Dependent Claim
16 words
A semiconductor wafer as in claim 3, wherein said plating comprises one of nickel and copper.
Claim 10
Dependent Claim
20 words
A semiconductor wafer as in claim 3, wherein said aluminum layer has a thickness of no greater than 1 micrometer.
Claim 11
Dependent Claim
18 words
A semiconductor wafer as in claim 3, wherein said plating has a thickness of at least 5 micrometers.
Claim 12
Dependent Claim
19 words
A semiconductor wafer as in claim 3, further comprising a gold layer between said bump electrode and said plating.
Claim 13
Dependent Claim
30 words
A semiconductor wafer as in claim 1, wherein each of said chip sections has a center and a periphery and said interconnection layers extend from said periphery toward said center.
Claim 14
Dependent Claim
16 words
A semiconductor wafer as in claim 4, wherein said plating comprises one of nickel and copper.
Claim 15
Dependent Claim
20 words
A semiconductor wafer as in claim 4, wherein said aluminum layer has a thickness of no greater than 1 micrometer.
Claim 16
Dependent Claim
18 words
A semiconductor wafer as in claim 4, wherein said plating has a thickness of at least 5 micrometers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-30 | 2002-06-01 | 2002-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-30 | 2006-06-01 | 2006-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-30 | 2010-06-01 | 2010-12-01 | $7700.00 | Window Closed / Lapsed |