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US5281151A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor chip carrier, module having same chip carrier mounted therein, and electronic device incorporating same module

Assignee: Hitachi Ltd
•
Filing: 1992-06-23
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Granted: 1994-01-25
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Expires: 2012-06-23
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Abstract

Abstract A semiconductor chip carrier, an electronic module having the semiconductor chip carrier mounted therein, and an electronic device incorporating the electronic module. A semiconductor chip carrier comprises a multi-layer wiring substrate including a multi-layer ceramic board, and a thin film circuit mounted on said multi-layer ceramic board, and a semiconductor chip mounted and connected to the thin film circuit, wherein a low-resistance conductor path is provided on the surface of or in the multi-layer wiring substrate to connect between signal terminals which need to be connected with a low-resistance wire in the semiconductor chip, thereby realizing signal transmission at low resistance between the signal terminals of the semiconductor chip by this conductor path. This arrangement makes it possible to shorten the signal delay time of a semiconductor chip, and achieve higher speed signal processing in modules and electronic equipment in which a thus-improved semiconductor chip is used.

Inventors

  • 👤 Hideo Arima
  • 👤 Kenji Takeda
  • 👤 Hideho Yamamura
  • 👤 Fumiyuki Kobayashi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 18:12
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/67; H10W70/68; H10W70/685; H10W70/686; H10W90/00; H10W70/62; H10W70/65; H10W70/654; H10W70/655; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W72/851; H10W72/874; H10W72/877; H10W90/20; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/734

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 72 words
In a semiconductor chip carrier comprising: a semiconductor chip mounted and connected to a multi-layer wiring substrate; a conductor path for connecting signal terminals in the semiconductor chip at electrically low resistance; means for securing the conductor path relative to said multi-layer wiring substrate such that the conductor path is provided in a position of at least one of (a) on said multi-layer wiring substrate, and (b) in said multi-layer wiring substrate.
Claim 2
Dependent Claim 72 words
In a semiconductor chip carrier comprising: a semiconductor chip mounted and connected to a multi-layer wiring substrate; a conductor path for connecting signal terminals in the semiconductor chip at electrically low resistance; means for securing the conductor path relative to said multi-layer wiring substrate such that the conductor path is provided in a position of at least one of (a) on said multi-layer wiring substrate, and (b) in said multi-layer wiring substrate.
Claim 3
Dependent Claim 63 words
A semiconductor chip carrier according to claim 1, wherein said multi-layer wiring substrate includes: a first multi-layer wiring substrate constituted by a multi-layer ceramic board; and a multi-layer wiring conductor constituted by a thin film circuit laminated and electrically connected to said first multi-layer wiring conductor; and wherein said semi conductor chip is mounted and electrically connected to said second multi-layer wiring conductor.
Claim 4
Dependent Claim 31 words
A semiconductor chip carrier according to claim 2, wherein layer insulating films of said second multi-layer wiring conductor constituted by said thin film circuit are comprised of heat-resistant organic insulating films.
Claim 5
Dependent Claim 20 words
A semiconductor chip carrier according to claim 3, wherein said heat-resistant organic insulating films are comprised of polyimide resin films.
Claim 6
Dependent Claim 60 words
A semiconductor chip carrier according to claim 1, wherein said conductor path includes a longest portion for connecting the signal terminals in said semiconductor chip at electrically low resistance, which longest portion is directed in parallel with the direction of a main wiring disposed at least one of inside said semiconductor chip and on the surface of said semiconductor chip.

References Cited (Backward Citations)

US5019945A Cited
US4924353A Cited
US4967314A Cited
US4937707A Cited
US5157589A Cited
US5165984A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-01-24 1997-07-26 1998-01-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-01-24 2001-07-26 2002-01-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-01-24 2005-07-26 2006-01-25 $7700.00 Window Closed / Lapsed

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