Semiconductor device including a substrate having clustered interconnects

Claim 2

A semiconductor device, comprising: a semiconductor die having a plurality of die terminals; and a substrate having a first surface on which is mounted the semiconductor die, a second surface opposite the first surface, and a plurality of interconnects including at least one signal interconnect and at least one supply interconnect, the semiconductor die being electrically connected to the plurality of interconnects through the plurality of die terminals, the plurality of interconnects routing through the substrate to the second surface on which are provided a plurality of substrate terminals that are spaced apart by a pitch P 1 , each interconnect of the plurality of interconnects having a first printed wire and an intermediate via thereby providing a plurality of first printed wires and a plurality of intermediate vias, each first printed wire of the plurality of first printed wires providing electrical connection between a respective intermediate via of the plurality of intermediate vias and a respective die terminal of the plurality of die terminals, wherein the plurality of intermediate vias are arranged in a cluster, adjacent intermediate vias of the plurality of intermediate vias in the cluster are spaced apart by a distance that is less than the pitch P 1 , and the cluster includes at least one signal intermediate via of the at least one signal interconnect and at least one supply intermediate via of the at least one supply interconnect.

Claim 3

The semiconductor device of claim 1, wherein each interconnect of the plurality of interconnects further comprises a second printed wire thereby providing a plurality of second printed wires, the plurality of second printed wires providing electrical connection between the plurality of intermediate vias and the plurality of substrate terminals.

Claim 4

The semiconductor device of claim 1, wherein each interconnect of the plurality of interconnects further comprises a die-scale via thereby providing a plurality of die-scale vias, the plurality of die-scale vias routing from the plurality of first printed wires to the plurality of die terminals.

Claim 5

The semiconductor device of claim 1, wherein each of the plurality of die terminals comprises a component from a group consisting of solder bumps and wire bonds.

Claim 6

The semiconductor device of claim 1, wherein each of the plurality of substrate terminals comprises a component from a group consisting of solder balls, pins, and lands.

Claim 7

The semiconductor device of claim 1, wherein the substrate is selected from the group consisting of an organic resin substrate, ceramic substrate, and an insulated metal core substrate.

Claim 8

The semiconductor device of claim 6, wherein a ratio of said distance to P 1 is within a range of approximately 2 to 10.

Claim 9

The semiconductor device of claim 1, wherein the plurality of intermediate vias are arranged in an array, the plurality of intermediate vias being spaced apart from each other by a pitch P 2 , wherein P 2 is equal to said distance and P 2 <P 1 .

Claim 10

The semiconductor device of claim 1, wherein the plurality of intermediate vias are arranged in a plurality of clusters.

Claim 11

The semiconductor device of claim 2, wherein each interconnect of the plurality of interconnects further comprises a package-scale via thereby providing a plurality of package-scale vias, the plurality of package-scale vias routing from the plurality of second printed wires to the plurality of substrate terminals.

Claim 12

The semiconductor device of claim 6, wherein the substrate is ceramic.

Claim 13

The semiconductor device of claim 8, wherein a ratio P 1 /P 2 is within a range of approximately 2 to 10.

Claim 14

The semiconductor device of claim 9, wherein the at least one supply interconnect includes a plurality of supply interconnects, the plurality of supply interconnects including a plurality of ground interconnects and a plurality of power interconnects, wherein the plurality of ground interconnects are electrically connected together to be at substantially a same potential, and the plurality of power interconnects are electrically connected together to be at substantially a same potential.

Claim 15

The semiconductor device of claim 13, wherein the plurality of ground interconnects are electrically connected together in the substrate by a common conductive plane.

Claim 16

The semiconductor device of claim 13, wherein the plurality of power interconnects are electrically connected together in the substrate by a common conductive plane.

Claim 17

A semiconductor device, comprising: a semiconductor die having a plurality of die terminals; a substrate having a first surface on which is mounted the semiconductor die, a second surface opposite the first surface, and a plurality of interconnects including signal interconnects and supply interconnects, the semiconductor die being electrically connected to the plurality of interconnects through the plurality of die terminals, the plurality of interconnects routing through the substrate to the second surface on which are provided a plurality of substrate terminals that are spaced apart by a pitch P 1 , each interconnect of the plurality of interconnects having a first printed wire, a second printed wire and an intermediate via thereby providing a plurality of first printed wires, a plurality of second printed wires and a plurality of intermediate vias, each first printed wire of the plurality of first printed wires electrically connecting a respective intermediate via of the plurality of intermediate vias to a respective die terminal of the plurality of die terminals, and each second printed wire of the plurality of second printed wires electrically connecting a respective intermediate via of the plurality of intermediate vias to a respective substrate terminal of the plurality of substrate terminals, wherein the plurality of intermediate vias are arranged in a plurality of clusters, adjacent intermediate vias of the plurality of intermediate vias in each cluster of the plurality of clusters being spaced apart by a distance that is less than the pitch P 1 , and each cluster of the plurality of clusters including at least one signal intermediate via and at least one supply intermediate via; and wherein the supply interconnects include ground interconnects and power interconnects, wherein the ground interconnects are electrically connected together to be at substantially a same potential by a common conductive plane, and the power interconnects are electrically connected together to be at substantially a same potential.

Claim 18

A semiconductor device, comprising: a semiconductor die having a plurality of die terminals; a substrate having a first surface on which is mounted the semiconductor die, a second surface opposite the first surface, and a plurality of interconnects including signal interconnects and supply interconnects, the semiconductor die being electrically connected to the plurality of interconnects through the plurality of die terminals, the plurality of interconnects routing through the substrate to the second surface on which are provided a plurality of substrate terminals that are spaced apart by a pitch P 1 , each interconnect of the plurality of interconnects having a first printed wire, a second printed wire and an intermediate via thereby providing a plurality of first printed wires, a plurality of second printed wires and a plurality of intermediate vias, each first printed wire of the plurality of first printed wires electrically connecting a respective intermediate via of the plurality of intermediate vias to a respective die terminal of the plurality of die terminals, and each second printed wire of the plurality of second printed wires electrically connecting a respective intermediate via of the plurality of intermediate vias to a respective substrate terminal of the plurality of substrate terminals, wherein the plurality of intermediate vias are arranged in a plurality of clusters, adjacent intermediate vias of the plurality of intermediate vias in each cluster of the plurality of clusters being spaced apart by a distance that is less than the pitch P 1 , and each cluster of the plurality of clusters including at least one signal intermediate via and at least one supply intermediate via; and wherein the supply interconnects include ground interconnects and power interconnects, wherein the ground interconnects are electrically connected together to be at substantially a same potential by a common conductive plane, and the power interconnects are electrically connected together to be at substantially a same potential.

Claim 19

The semiconductor device of claim 16, wherein each interconnect of the plurality of interconnects further comprises a package-scale via thereby providing a plurality of package-scale vias, the plurality of package-scale vias routing from the plurality of second printed wires to the plurality of substrate terminals.

Claim 20

The semiconductor device of claim 16, wherein each interconnect of the plurality of interconnects further comprises a die-scale via thereby providing a plurality of die-scale vias, the plurality of die-scale vias routing from the plurality of first printed wires to the plurality of die terminals.

Claim 21

The semiconductor device of claim 16, wherein each of the plurality of die terminals comprises a component from a group consisting of solder bumps and wire bonds.

Claim 22

The semiconductor device of claim 16, wherein each of the plurality of substrate terminals comprises a component from a group consisting of solder balls, pins, and lands.

Claim 23

The semiconductor device of claim 16, wherein the substrate is selected from the group consisting of an organic resin substrate, a ceramic substrate, and an insulated metal core substrate.

Claim 24

The semiconductor device of claim 16, wherein a ratio of said distance to P 2 is within a range of approximately 2 to 10.

Claim 25

The semiconductor device of claim 16, wherein the plurality of intermediate vias in said each cluster are arranged in an array, the plurality of intermediate vias being spaced apart from each other by a pitch P 2 , wherein P 2 is equal to said distance and P 2 <P 1 .

Claim 26

The semiconductor device of claim 16, wherein the power interconnects are electrically connected together in the substrate by a common conductive plane.

Claim 27

The semiconductor device of claim 21, wherein the substrate is ceramic.

Claim 28

The semiconductor device of claim 23, wherein a ratio P 1 /P 2 is within a range of approximately 2 to 10.