Patent CA515868A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5708296A Expired / Lapsed US ⏱️ 0.0 years remaining

Power-ground plane for a C4 flip-chip substrate

Assignee: Intel Corp
•
Filing: 1996-06-24
•
Granted: 1998-01-13
•
Expires: 2016-06-24
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A package for an integrated circuit that contains a plurality of small circular dielectric spaces which separate vias from a conductive plane of the package. The package has a first internal conductive plane, a second internal conductive plane and a plurality of bond pads located on a top surface of a substrate. The substrate has a plurality of vias that extend through the first conductive plane to couple the second conductive plane to the bond pads. The package has a plurality of concentric dielectric clearance spaces that separate the vias from the first conductive plane. The small concentric spaces optimize the area of the conductive plane to minimize the resistance and maximize the capacitance of the package.

Inventors

  • 👤 Ameet Bhansali

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 23:10
CPC Classifications
H; H10; H10W; H10W72/00; H05; H05K; H05K1/00; H05K1/02; H05K1/0213; H05K1/0216; H05K1/0218; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/63; H10W70/635; H10W70/67; H10W70/68; H10W70/685; H10W72/071; H10W72/072; H10W72/07251; H10W72/20

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 129 words
An electronic package, comprising: a substrate that has a first conductive plane, a second conductive plane, a layer of signal routing traces and a plurality of bond pads located on a top surface of said substrate, said first conductive plane being separated from said second conductive plane by a first dielectric space and said layer of signal routing traces being separated from said second conductive plane by a second dielectric space that has a width which is greater than a width of said first dielectric space, said substrate having a plurality of vias that extend through said first conductive plane and couple said second conductive plane with said bond pads, said substrate further having a plurality of circular clearance spaces that separate said vias from said first conductive plane.
Claim 2
Dependent Claim 129 words
An electronic package, comprising: a substrate that has a first conductive plane, a second conductive plane, a layer of signal routing traces and a plurality of bond pads located on a top surface of said substrate, said first conductive plane being separated from said second conductive plane by a first dielectric space and said layer of signal routing traces being separated from said second conductive plane by a second dielectric space that has a width which is greater than a width of said first dielectric space, said substrate having a plurality of vias that extend through said first conductive plane and couple said second conductive plane with said bond pads, said substrate further having a plurality of circular clearance spaces that separate said vias from said first conductive plane.
Claim 3
Dependent Claim 50 words
The package as recited in claim 1, wherein said substrate has a plurality of vias that extend through said second conductive plane to connect said first conductive plane to a third conductive plane wherein said vias are separated from said second conductive plane by a plurality of circular clearance spaces.
Claim 4
Dependent Claim 25 words
The package as recited in claim 2, wherein said substrate has a plurality of vias that connect said first conductive plane to said bond pads.
Claim 5
Dependent Claim 24 words
The package as recited in claim 1, wherein said first layer of signal routing traces are coupled to said bond pads by said vias.
Claim 6
Dependent Claim 30 words
The package as recited in claim 3, further comprising a capacitor that is mounted to said top surface of said substrate and coupled to said first and second conductive planes.
Claim 7
Dependent Claim 27 words
The package as recited in claim 3, wherein said first conductive plane is dedicated to electrical power and said second conductive plane is dedicated to electrical ground.
Claim 8
Dependent Claim 21 words
The package as recited in claim 1, wherein said vias are arranged in a two dimensional array of rows and columns.
Claim 9
Dependent Claim 143 words
An electronic package, comprising: a substrate that has a first conductive plane, a second conductive plane, a layer of signal routing traces and a plurality of bond pads located on a top surface of said substrate, said first conductive plane being separated from said second conductive plane by a first dielectric space and said layer of signal routing traces being separated from said second conductive plane by a second dielectric space that has a width which is greater than a width of said first dielectric space, said substrate having a plurality of vias that extend through said first conductive plane and couple said second conductive plane with said bond pads, said substrate further having a plurality of circular clearance spaces that separate said vias from said first conductive plane; and, an integrated circuit that is mounted to said top surface of said substrate.
Claim 10
Dependent Claim 143 words
An electronic package, comprising: a substrate that has a first conductive plane, a second conductive plane, a layer of signal routing traces and a plurality of bond pads located on a top surface of said substrate, said first conductive plane being separated from said second conductive plane by a first dielectric space and said layer of signal routing traces being separated from said second conductive plane by a second dielectric space that has a width which is greater than a width of said first dielectric space, said substrate having a plurality of vias that extend through said first conductive plane and couple said second conductive plane with said bond pads, said substrate further having a plurality of circular clearance spaces that separate said vias from said first conductive plane; and, an integrated circuit that is mounted to said top surface of said substrate.
Claim 11
Dependent Claim 50 words
The package as recited in claim 8, wherein said substrate has a plurality of vias that extend through said second conductive plane to connect said first conductive plane to a third conductive plane wherein said vias are separated from said second conductive plane by a plurality of circular clearance spaces.
Claim 12
Dependent Claim 25 words
The package as recited in claim 9, wherein said substrate has a plurality of vias that connect said first conductive plane to said bond pads.
Claim 13
Dependent Claim 21 words
The package as recited in claim 8, wherein said signal routing traces are coupled to said bond pads by said vias.
Claim 14
Dependent Claim 30 words
The package as recited in claim 10, further comprising a capacitor that is mounted to said top surface of said substrate and coupled to said first and second conductive planes.
Claim 15
Dependent Claim 27 words
The package as recited in claim 10, wherein said first conductive plane is dedicated to electrical power and said second conductive plane is dedicated to electrical ground.
Claim 16
Dependent Claim 21 words
The package as recited in claim 8, wherein said vias are arranged in a two dimensional array of rows and columns.

References Cited (Backward Citations)

US4667219A Cited
US5450290A Cited
US5538433A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-01-12 2001-07-14 2002-01-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-01-12 2005-07-14 2006-01-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-01-12 2009-07-14 2010-01-13 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag