US5714801A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor package
Assignee: Toshiba Corp
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Filing: 1996-03-29
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Granted: 1998-02-03
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Expires: 2016-03-29
Abstract
Abstract A semiconductor package is disclosed which is provided with a multilayer ceramic substrate such as, for example, a multilayer aluminum nitride substrate having a surface for mounting a semiconductor device and, at the same time, having an inner wiring layer electrically connected to the semiconductor device. On the surface of the multilayer ceramic substrate for forming terminals thereon, input and output terminals such as, for example, pin terminals and bump terminals electrically connected to the inner wiring layer. The input and output terminals embrace signal terminals, ground terminals, and power source terminals. The signal terminals among other terminals are so disposed that they may be each positioned adjacently to at least one ground terminal or power source terminal. This semiconductor package possesses perfect transmission properties even for signals of such a high frequency as exceeds the order of GHz. The dispersion of the transmission properties is small.
Inventors
- 👤 Keiichi Yano
- 👤 Jun-ichi Kudo
- 👤 Koji Yamakawa
- 👤 Kiyoshi Iyogi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 12:48
CPC Classifications
H; H10; H10W; H10W74/00; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/685; H10W70/62; H10W70/65; H10W70/654; H10W70/655; H10W72/00; H10W72/50; H10W72/531; H10W72/5363; H10W90/00; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
110 words
A semiconductor package comprising: a multilayer ceramic substrate having an upper surface for mounting a semi-conductor device thereon, a lower surface for forming a plurality of input and output terminals thereon and an inner wiring layer electrically connected to said semiconductor device, and wherein the plurality of input and output terminals are electrically connected to said inner wiring layer, the plurality of input and output terminals comprising: signal terminals, ground terminals, and power source terminals disposed on the lower surface of said multilayer ceramic substrate and wherein at least half of said signal terminals are disposed adjacent to at least one of the ground terminals and the power source terminals.
Claim 2
Dependent Claim
110 words
A semiconductor package comprising: a multilayer ceramic substrate having an upper surface for mounting a semi-conductor device thereon, a lower surface for forming a plurality of input and output terminals thereon and an inner wiring layer electrically connected to said semiconductor device, and wherein the plurality of input and output terminals are electrically connected to said inner wiring layer, the plurality of input and output terminals comprising: signal terminals, ground terminals, and power source terminals disposed on the lower surface of said multilayer ceramic substrate and wherein at least half of said signal terminals are disposed adjacent to at least one of the ground terminals and the power source terminals.
Claim 3
Dependent Claim
28 words
The semiconductor package according to claim 1, wherein all said signal terminals are disposed adjacently to at least one of said ground terminals or said power source terminals.
Claim 4
Dependent Claim
49 words
The semiconductor package according to claim 1, wherein said input and output terminals are arranged on the lower surface of said multilayer ceramic substrate in a latticelike pattern and at least one terminal adjacent to every signal terminal is one of said ground terminals and said power source terminals.
Claim 5
Dependent Claim
58 words
The semiconductor package according to claim 1, wherein said inner wiring layer has a multilayered structure comprising a signal wiring layer, a ground wiring layer, and a power source wiring layer, said signal wiring layer and at least one of said ground wiring layer and said power source wiring layer are alternately superposed to form said multilayered structure.
Claim 6
Dependent Claim
18 words
The semiconductor package according to claim 1, wherein said multilayer ceramic substrate is a multilayer aluminum nitride substrate.
Claim 7
Dependent Claim
19 words
The semiconductor package according to claim 1, wherein said input and output terminals are pin terminals or bump terminals.
Claim 8
Dependent Claim
177 words
A semiconductor package comprising: a multilayer ceramic substrate having an upper surface for mounting a semiconductor device thereon and a lower surface for forming terminals thereon, a multilayered inner wiring layer disposed in said multilayer ceramic substrate said inner wiring layer comprising a signal wiring layer, a ground wiring layer, and a power source wiring layer, wherein at least either of said ground wiring layer and said power source wiring layer is planarly formed in said multilayer ceramic substrate, ground terminals electrically connected to said ground wiring layer and disposed on the lower surface of said multilayer ceramic substrate for forming terminals thereon, power source terminals electrically connected to said power source wiring layer and disposed on the lower surface of said multilayer ceramic substrate for forming terminals thereon, and signal terminals electrically connected to said signal wiring layer and disposed on the lower surface of said multilayer ceramic substrate for forming terminals thereon, wherein at least half of said signal terminals are adjacent to at least one of the ground terminals and the power source terminals.
Claim 9
Dependent Claim
177 words
A semiconductor package comprising: a multilayer ceramic substrate having an upper surface for mounting a semiconductor device thereon and a lower surface for forming terminals thereon, a multilayered inner wiring layer disposed in said multilayer ceramic substrate said inner wiring layer comprising a signal wiring layer, a ground wiring layer, and a power source wiring layer, wherein at least either of said ground wiring layer and said power source wiring layer is planarly formed in said multilayer ceramic substrate, ground terminals electrically connected to said ground wiring layer and disposed on the lower surface of said multilayer ceramic substrate for forming terminals thereon, power source terminals electrically connected to said power source wiring layer and disposed on the lower surface of said multilayer ceramic substrate for forming terminals thereon, and signal terminals electrically connected to said signal wiring layer and disposed on the lower surface of said multilayer ceramic substrate for forming terminals thereon, wherein at least half of said signal terminals are adjacent to at least one of the ground terminals and the power source terminals.
Claim 10
Dependent Claim
28 words
The semiconductor package according to claim 7, wherein all said signal terminals are disposed adjacently to at least one of said ground terminals or said power source terminals.
Claim 11
Dependent Claim
55 words
The semiconductor package according to claim 7, wherein said ground terminals, said power source terminals, and said signal terminals are arranged on the lower surface of said multilayer ceramic substrate in a latticelike pattern and at least one terminal adjacent to every signal terminal is one of said ground terminals and said power source terminals.
Claim 12
Dependent Claim
34 words
The semiconductor package according to claim 7, wherein said signal wiring layer and either of said ground wiring layer and said power source wiring layer are alternately superposed to form said multilayer ceramic substrate.
Claim 13
Dependent Claim
18 words
The semiconductor package according to claim 7, wherein said multilayer ceramic substrate is a multilayer aluminum nitride substrate.
Claim 14
Dependent Claim
25 words
The semiconductor package according to claim 7, wherein said ground terminals, said power source terminals, and said signal terminals are pin terminals or bump terminals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-02 | 2001-08-04 | 2002-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-02 | 2005-08-04 | 2006-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-02 | 2009-08-04 | 2010-02-03 | $7700.00 | Window Closed / Lapsed |