Multilayer interconnection substrate and semiconductor integrated circuit device using the same

Claim 2

A multilayer interconnection substrate having a component mounting surface for mounting components thereon, comprising: signal layers; power supply layers; at least one power supply matching layer, layered above both the signal layers and the power supply layers and close to the component mounting surface; each power supply matching layer being provided to correspond to respective voltages of the components to be mounted to the component mounting surface; insulating layers for electrically insulating the signal layers, the power supply layers and the power supply matching layer from each other; said signal layers, said power supply layers, said power supply matching layer and the insulating layers being superposed into a laminate; component connection terminal means, mounted to the component mounting surface, for connection to the component; said component connection terminal means including component power supply terminals; external connection terminal means mounted to another surface of the multilayer interconnection substrate; said external connection terminal means including external power supply terminals; and interconnecting means including: first power supply interconnection means for interconnecting said at least one power supply matching layer to corresponding component power supply terminals; second power supply interconnection means for interconnecting the power supply matching layer to corresponding power supply layers; and third power supply interconnection means for interconnecting said at least one power supply matching layer to corresponding external power supply terminals.

Claim 3

A multilayer interconnection substrate according to Claim 1, wherein: the signal layers, the power supply layers and the power supply matching layer have each a corresponding conductor pattern sandwiched between adjacent insulating layers; and the interconnecting means comprises through holes formed through at least some of the insulating layers.

Claim 4

A multilayer interconnection substrate having component mounting surfaces for mounting components thereon, comprising: signal layers; power supply layers; at least two power supply matching layers which are respectively layered above and below both the signal layers and the power supply layers and close to the component mounting surfaces; each power supply matching layer being provided to correspond to respective voltages of the components to be mounted to the component mounting surfaces; insulating layers for electrically insulating the signal layers, the power supply layers and the power supply matching layer from each other; said signal layers, said power supply layers, said power supply matching layers and the insulating layers being superposed into a laminate; component connection terminal means, mounted to the component mounting surfaces, respectively, for connection to the components; said component connection terminal means including component power supply terminals; external connection terminal means mounted to another surface of the multilayer interconnection substrate; said external connection terminal means including external power supply terminals; and interconnecting means including: first power supply interconnection means for interconnecting said power supply matching layers to corresponding component power supply terminals; second power supply interconnection means for interconnecting the power supply matching layer to corresponding power supply layers; and third power supply interconnection means for interconnecting said power supply matching layer to corresponding external power supply terminals.

Claim 5

A multilayer interconnection substrate having component mounting surfaces for mounting components thereon, comprising: signal layers; power supply layers; at least two power supply matching layers which are respectively layered above and below both the signal layers and the power supply layers and close to the component mounting surfaces; each power supply matching layer being provided to correspond to respective voltages of the components to be mounted to the component mounting surfaces; insulating layers for electrically insulating the signal layers, the power supply layers and the power supply matching layer from each other; said signal layers, said power supply layers, said power supply matching layers and the insulating layers being superposed into a laminate; component connection terminal means, mounted to the component mounting surfaces, respectively, for connection to the components; said component connection terminal means including component power supply terminals; external connection terminal means mounted to another surface of the multilayer interconnection substrate; said external connection terminal means including external power supply terminals; and interconnecting means including: first power supply interconnection means for interconnecting said power supply matching layers to corresponding component power supply terminals; second power supply interconnection means for interconnecting the power supply matching layer to corresponding power supply layers; and third power supply interconnection means for interconnecting said power supply matching layer to corresponding external power supply terminals.

Claim 6

A multilayer interconnection substrate according to Claim 3, wherein: the component connection terminal means comprises signal terminals; the external connection terminal means comprises external signal terminals; and the interconnecting means comprises: first signal interconnection means for interconnecting the signal terminals of the component connection terminal means to corresponding signal layers; and second signal interconnection means for interconnecting the signal terminals of the external connection terminal means to corresponding signal layers.

Claim 7

A multilayer interconnection substrate according to Claim 4, further comprising: an external connector adapted to connect to the external power supply terminals and the external signal terminals; said external connector being mounted to the another surface of the multilayer interconnection substrate.

Claim 8

A multilayer interconnection substrate according to Claim 1 wherein: the component connection terminal means comprises signal terminals; the external connection terminal means comprises external signal terminals; and the interconnecting means comprises: first signal interconnection means for interconnecting the signal terminals of the component connection terminal means to corresponding signal layers; and second signal interconnection means for interconnecting the external signal terminals of the external connection terminal means to corresponding signal layers, and further comprising: I/O pins connected to respective external signal terminals and external power supply terminals.

Claim 9

a multilayer interconnection substrate according to Claim 1, wherein: the component connection terminal means comprises signal terminals; the external connection terminal means comprises external signal terminals; and the interconnecting means comprises: first signal interconnection means for interconnecting the signal terminals of the component connection terminal means to corresponding signal layers; and second signal interconnection means for interconnecting the external signal terminals of the external connection terminal means to corresponding signal layers; and wherein: both the signal terminals and the power supply terminals of the component connection terminal means are separated in groups, each group being arranged at a corresponding chip site on the component mounting surface, the chip site being adapted to have a corresponding component mounted thereat.

Claim 10

A multilayer interconnection substrate according to Claim 7, wherein the first power supply interconnection means and the first signal interconnection means have each the same arrangement pattern as to every group of component connection terminal means.

Claim 11

A chip carrier having opposite surfaces, one surface being adapted to support a semiconductor chip, the chip carrier comprising: at least one power supply matching layer corresponding in voltage to the semiconductor chip; insulating layers sandwiching the power supply matching layer, the insulating layers and power supply matching layer being superposed; chip connection terminal means, mounted on one surface of the chip carrier, for connection to the semiconductor chip, the chip connection terminal means including chip power supply terminals; substrate connection terminal means, mounted on the other surface of the chip carrier, for connection to a multilayer interconnection substrate, the substrate connection terminal means including substrate power supply terminals; and interconnecting means for interconnecting each of both the chip power supply terminals and the substrate power supply terminals to a corresponding power supply matching layer.

Claim 12

A chip carrier having opposite surfaces, one surface being adapted to support a semiconductor chip, the chip carrier comprising: at least one power supply matching layer corresponding in voltage to the semiconductor chip; insulating layers sandwiching the power supply matching layer, the insulating layers and power supply matching layer being superposed; chip connection terminal means, mounted on one surface of the chip carrier, for connection to the semiconductor chip, the chip connection terminal means including chip power supply terminals; substrate connection terminal means, mounted on the other surface of the chip carrier, for connection to a multilayer interconnection substrate, the substrate connection terminal means including substrate power supply terminals; and interconnecting means for interconnecting each of both the chip power supply terminals and the substrate power supply terminals to a corresponding power supply matching layer.

Claim 13

A semiconductor integrated circuit device including a semiconductor chip, a chip carrier for supporting the semiconductor chip; and a multilayer interconnection substrate having the chip carrier mounted thereon, wherein: the chip carrier has opposite surfaces, one surface thereof having the semiconductor chip mounted thereon; the chip carrier comprises: at least one power supply matching layer corresponding in voltage to the semiconductor chip; insulating layers sandwiching the power supply matching layer, the insulating layers and power supply matching layer being superposed; chip connection terminal means, mounted on one surface of the chip carrier, for connecting to the semiconductor chip, the chip connection terminal means including chip power supply terminals; substrate connection terminal means, mounted on the other surface of the chip carrier, for connecting to the multilayer interconnection substrate, the substrate connection terminal means including substrate power supply terminals; and interconnecting means for interconnecting each of both the chip power supply terminals and the substrate power supply terminals to the power supply matching layer.

Claim 14

A semiconductor integrated circuit device including a semiconductor chip, a chip carrier for supporting the semiconductor chip; and a multilayer interconnection substrate having the chip carrier mounted thereon, wherein: the chip carrier has opposite surfaces, one surface thereof having the semiconductor chip mounted thereon; the chip carrier comprises: at least one power supply matching layer corresponding in voltage to the semiconductor chip; insulating layers sandwiching the power supply matching layer, the insulating layers and power supply matching layer being superposed; chip connection terminal means, mounted on one surface of the chip carrier, for connecting to the semiconductor chip, the chip connection terminal means including chip power supply terminals; substrate connection terminal means, mounted on the other surface of the chip carrier, for connecting to the multilayer interconnection substrate, the substrate connection terminal means including substrate power supply terminals; and interconnecting means for interconnecting each of both the chip power supply terminals and the substrate power supply terminals to the power supply matching layer.

Claim 15

In a semiconductor integrated circuit device including a semiconductor chip and a multilayer interconnection substrate for supporting the semiconductor chip, the multilayer interconnection substrate having a chip mounting surface, the multilayer interconnection substrate comprising: signal layers; a power supply layers; at least one power supply matching layer, layered above both the signal layers and the power supply layers and close to the chip mounting surface, the power supply matching layer corresponding in voltage to the semiconductor chip; insulating layers for electrically insulating the signal layers, the power supply layers and the power supply matching layer from each other, the signal layers, the power supply layers, the power supply matching layer and the insulating layers being superposed; component connection terminal means, mounted to the component mounting surface for connecting to the semiconductor chip, the component connection terminal means including component power supply terminals; external connection terminal means mounted to another surface of the multilayer interconnection substrate, the external connection terminal means including signal I/O pins and power supply I/O pins; and interconnecting means including first power supply interconnection means for interconnecting the power supply matching layer to corresponding component power supply terminals, second power supply interconnection means for interconnecting the power supply matching layer to corresponding power supply layers, and third power supply interconnection means for interconnecting the power supply matching layer to corresponding power supply I/O pins.

Claim 16

In a semiconductor integrated circuit device including a semiconductor chip and a multilayer interconnection substrate for supporting the semiconductor chip, the multilayer interconnection substrate having a chip mounting surface, the multilayer interconnection substrate comprising: signal layers; a power supply layers; at least one power supply matching layer, layered above both the signal layers and the power supply layers and close to the chip mounting surface, the power supply matching layer corresponding in voltage to the semiconductor chip; insulating layers for electrically insulating the signal layers, the power supply layers and the power supply matching layer from each other, the signal layers, the power supply layers, the power supply matching layer and the insulating layers being superposed; component connection terminal means, mounted to the component mounting surface for connecting to the semiconductor chip, the component connection terminal means including component power supply terminals; external connection terminal means mounted to another surface of the multilayer interconnection substrate, the external connection terminal means including signal I/O pins and power supply I/O pins; and interconnecting means including first power supply interconnection means for interconnecting the power supply matching layer to corresponding component power supply terminals, second power supply interconnection means for interconnecting the power supply matching layer to corresponding power supply layers, and third power supply interconnection means for interconnecting the power supply matching layer to corresponding power supply I/O pins.

Claim 17

A semiconductor integrated circuit device according to Claim 11, wherein: the signal layers, the power supply layers and the power supply matching layer have each a corresponding conductor pattern sandwiched between adjacent insulating layers; and the interconnecting means comprises through holes formed through at least some of the insulating layers.

Claim 18

A multilayer interconnection substrate having a chip mounting surface, the multilayer interconnection substrate comprises: signal layers; power supply layers; at least one power supply matching layer, layered above both the signal layers and the power supply layers and close to the chip mounting surface, the power supply matching layer corresponding in voltage to a semiconductor chip to be mounted on the chip mounting surface; insulating layers for electrically insulating the signal layers, the power supply layers and the power supply matching layer from each other, the signal layers, the power supply layers, the power supply matching layer and the insulating layers being superposed; component connection terminal means, mounted to the component mounting surface for connecting to the semiconductor chip, the component connection terminal means including component power supply terminals; external connection terminal means mounted to another surface of the multilayer interconnection substrate, the external connection terminal means including signal I/O pins and power supply I/O pins; and interconnecting means including first power supply interconnection means for interconnecting the power supply matching layer to corresponding component power supply terminals, second power supply interconnection means for interconnecting the power supply matching layer to corresponding power supply layers, and third power supply interconnection means for interconnecting the power supply matching layer to corresponding power supply I/O pins.

Claim 19

A multilayer interconnection substrate having a chip mounting surface, the multilayer interconnection substrate comprises: signal layers; power supply layers; at least one power supply matching layer, layered above both the signal layers and the power supply layers and close to the chip mounting surface, the power supply matching layer corresponding in voltage to a semiconductor chip to be mounted on the chip mounting surface; insulating layers for electrically insulating the signal layers, the power supply layers and the power supply matching layer from each other, the signal layers, the power supply layers, the power supply matching layer and the insulating layers being superposed; component connection terminal means, mounted to the component mounting surface for connecting to the semiconductor chip, the component connection terminal means including component power supply terminals; external connection terminal means mounted to another surface of the multilayer interconnection substrate, the external connection terminal means including signal I/O pins and power supply I/O pins; and interconnecting means including first power supply interconnection means for interconnecting the power supply matching layer to corresponding component power supply terminals, second power supply interconnection means for interconnecting the power supply matching layer to corresponding power supply layers, and third power supply interconnection means for interconnecting the power supply matching layer to corresponding power supply I/O pins.

Claim 20

A multilayer interconnection substrate having a component mounting surface for mounting components thereon, comprising: signal layers; power supply layers; a bus-bar layer or layers, provided in the number corresponding to varieties of voltages which are required by the components to be mounted on the component mounting surface, for supplying power of the required voltages to the respective components; insulating layers for electrically insulating the layers from each other; the signal layers, the power supply layers, the bus-bar layers and the insulating layers being superposed into a laminate; and interconnecting means for interconnecting the power supplying layer or layers of the same voltage with the corresponding bus-bar layers, respectively.

Claim 21

A multilayer interconnection substrate having a component mounting surface for mounting components thereon, comprising: signal layers; power supply layers; a bus-bar layer or layers, provided in the number corresponding to varieties of voltages which are required by the components to be mounted on the component mounting surface, for supplying power of the required voltages to the respective components; insulating layers for electrically insulating the layers from each other; the signal layers, the power supply layers, the bus-bar layers and the insulating layers being superposed into a laminate; and interconnecting means for interconnecting the power supplying layer or layers of the same voltage with the corresponding bus-bar layers, respectively.

Claim 22

A multilayer interconnection substrate having a surface for mounting components thereon, comprising: signal layers; power supply layers adapted to have voltages desired by the respective components; bus-bar layers provided for the respective voltages and electrically connected to the power supply layers of the corresponding voltages, respectively, for supplying the power of desired voltages to the components through the bus-bar layers of the corresponding voltages, respectively; and insulation layers; said signal layers, said power supply layers and said bus-­bar layers being superposed into a laminate, while interposing the insulation layers between any two adjacent layers.

Claim 23

A multilayer interconnection substrate having a surface for mounting components thereon, comprising: signal layers; power supply layers adapted to have voltages desired by the respective components; bus-bar layers provided for the respective voltages and electrically connected to the power supply layers of the corresponding voltages, respectively, for supplying the power of desired voltages to the components through the bus-bar layers of the corresponding voltages, respectively; and insulation layers; said signal layers, said power supply layers and said bus-­bar layers being superposed into a laminate, while interposing the insulation layers between any two adjacent layers.